Lines Matching +full:protect +full:- +full:exec
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
29 #include "hw/qdev-properties.h"
30 #include "exec/exec-all.h"
31 #include "exec/cpu_ldst.h"
32 #include "exec/gdbstub.h"
33 #include "fpu/softfloat-helpers.h"
85 cpu->env.pc = value; in mb_cpu_set_pc()
87 cpu->env.iflags = 0; in mb_cpu_set_pc()
94 return cpu->env.pc; in mb_cpu_get_pc()
103 cpu->env.pc = tb->pc; in mb_cpu_synchronize_from_tb()
104 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; in mb_cpu_synchronize_from_tb()
113 cpu->env.pc = data[0]; in mb_restore_state_to_opc()
114 cpu->env.iflags = data[1]; in mb_restore_state_to_opc()
119 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); in mb_cpu_has_work()
128 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { in mb_cpu_mmu_index()
132 if (env->msr & MSR_UM) { in mb_cpu_mmu_index()
142 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; in mb_cpu_ns_axi_dp()
144 cpu->ns_axi_dp = level & en; in mb_cpu_ns_axi_dp()
150 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; in mb_cpu_ns_axi_ip()
152 cpu->ns_axi_ip = level & en; in mb_cpu_ns_axi_ip()
158 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; in mb_cpu_ns_axi_dc()
160 cpu->ns_axi_dc = level & en; in mb_cpu_ns_axi_dc()
166 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; in mb_cpu_ns_axi_ic()
168 cpu->ns_axi_ic = level & en; in mb_cpu_ns_axi_ic()
190 CPUMBState *env = &cpu->env; in mb_cpu_reset_hold()
192 if (mcc->parent_phases.hold) { in mb_cpu_reset_hold()
193 mcc->parent_phases.hold(obj, type); in mb_cpu_reset_hold()
197 env->res_addr = RES_ADDR_NONE; in mb_cpu_reset_hold()
200 env->shr = ~0; in mb_cpu_reset_hold()
202 env->pc = cpu->cfg.base_vectors; in mb_cpu_reset_hold()
204 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); in mb_cpu_reset_hold()
209 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); in mb_cpu_reset_hold()
216 mmu_init(&env->mmu); in mb_cpu_reset_hold()
222 info->mach = bfd_arch_microblaze; in mb_disas_set_info()
223 info->print_insn = print_insn_microblaze; in mb_disas_set_info()
242 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { in mb_cpu_realizefn()
243 error_setg(errp, "addr-size %d is out of range (32 - 64)", in mb_cpu_realizefn()
244 cpu->cfg.addr_size); in mb_cpu_realizefn()
250 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; in mb_cpu_realizefn()
259 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); in mb_cpu_realizefn()
262 cpu->cfg.pvr_regs[0] = in mb_cpu_realizefn()
266 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | in mb_cpu_realizefn()
267 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | in mb_cpu_realizefn()
268 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | in mb_cpu_realizefn()
269 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | in mb_cpu_realizefn()
270 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | in mb_cpu_realizefn()
271 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | in mb_cpu_realizefn()
272 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | in mb_cpu_realizefn()
274 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | in mb_cpu_realizefn()
275 cpu->cfg.pvr_user1); in mb_cpu_realizefn()
277 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; in mb_cpu_realizefn()
279 cpu->cfg.pvr_regs[2] = in mb_cpu_realizefn()
285 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | in mb_cpu_realizefn()
286 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | in mb_cpu_realizefn()
287 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | in mb_cpu_realizefn()
288 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | in mb_cpu_realizefn()
289 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | in mb_cpu_realizefn()
290 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | in mb_cpu_realizefn()
291 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | in mb_cpu_realizefn()
292 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | in mb_cpu_realizefn()
293 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | in mb_cpu_realizefn()
294 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | in mb_cpu_realizefn()
295 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | in mb_cpu_realizefn()
296 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | in mb_cpu_realizefn()
297 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | in mb_cpu_realizefn()
298 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); in mb_cpu_realizefn()
300 cpu->cfg.pvr_regs[5] |= in mb_cpu_realizefn()
301 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; in mb_cpu_realizefn()
303 cpu->cfg.pvr_regs[10] = in mb_cpu_realizefn()
305 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); in mb_cpu_realizefn()
307 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | in mb_cpu_realizefn()
310 cpu->cfg.mmu = 3; in mb_cpu_realizefn()
311 cpu->cfg.mmu_tlb_access = 3; in mb_cpu_realizefn()
312 cpu->cfg.mmu_zones = 16; in mb_cpu_realizefn()
313 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); in mb_cpu_realizefn()
315 mcc->parent_realize(dev, errp); in mb_cpu_realizefn()
324 gdb_find_static_feature("microblaze-stack-protect.xml"), in mb_cpu_initfn()
336 /* Restricted 'endianness' property is equivalent of 'little-endian' */ in mb_cpu_initfn()
337 object_property_add_alias(obj, "little-endian", obj, "endianness"); in mb_cpu_initfn()
345 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
346 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
349 * This is the C_ADDR_SIZE synth-time configuration option of the
355 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
356 /* If use-fpu > 0 - FPU is enabled
357 * If use-fpu = 2 - Floating point conversion and square root instructions
360 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
361 /* If use-hw-mul > 0 - Multiplier is enabled
362 * If use-hw-mul = 2 - 64-bit multiplier is enabled
364 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
365 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
366 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
367 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
368 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
369 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
371 * use-non-secure enables/disables the use of the non_secure[3:0] signals.
372 * It is a bitfield where 1 = non-secure for the following bits and their
374 * 0x1 - M_AXI_DP
375 * 0x2 - M_AXI_IP
376 * 0x4 - M_AXI_DC
377 * 0x8 - M_AXI_IC
379 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
380 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
384 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
387 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
389 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
391 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
393 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
395 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
399 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
400 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
413 #include "hw/core/sysemu-cpu-ops.h"
420 #include "hw/core/tcg-cpu-ops.h"
445 &mcc->parent_realize); in mb_cpu_class_init()
447 &mcc->parent_phases); in mb_cpu_class_init()
449 cc->class_by_name = mb_cpu_class_by_name; in mb_cpu_class_init()
450 cc->has_work = mb_cpu_has_work; in mb_cpu_class_init()
451 cc->mmu_index = mb_cpu_mmu_index; in mb_cpu_class_init()
452 cc->dump_state = mb_cpu_dump_state; in mb_cpu_class_init()
453 cc->set_pc = mb_cpu_set_pc; in mb_cpu_class_init()
454 cc->get_pc = mb_cpu_get_pc; in mb_cpu_class_init()
455 cc->gdb_read_register = mb_cpu_gdb_read_register; in mb_cpu_class_init()
456 cc->gdb_write_register = mb_cpu_gdb_write_register; in mb_cpu_class_init()
459 dc->vmsd = &vmstate_mb_cpu; in mb_cpu_class_init()
460 cc->sysemu_ops = &mb_sysemu_ops; in mb_cpu_class_init()
463 cc->gdb_core_xml_file = "microblaze-core.xml"; in mb_cpu_class_init()
465 cc->disas_set_info = mb_disas_set_info; in mb_cpu_class_init()
466 cc->tcg_ops = &mb_tcg_ops; in mb_cpu_class_init()