Lines Matching +full:7 +full:c80
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
58 #define QREG_SP get_areg(s, 7)
666 switch ((ext >> pos) & 7) { in ext_opsize()
732 if (reg0 == 7 && opsize == OS_BYTE && in gen_lea_mode()
748 case 7: /* Other */ in gen_lea_mode()
819 if (reg0 == 7 && opsize == OS_BYTE && in gen_ea_mode()
860 case 7: /* Other */ in gen_ea_mode()
1107 case 7: /* Other */ in gen_ea_mode_fp()
1201 case 7: /* EQ */ in gen_cc_cond()
1262 case 7: /* EQ (Z) */ in gen_cc_cond()
1315 case 7: /* EQ (Z) */ in gen_cc_cond()
1878 tcg_gen_andi_i32(src2, DREG(insn, 9), 7); in DISAS_INSN()
1932 return cpu_aregs[reg & 7]; in mreg()
2117 bitnum &= 7; in DISAS_INSN()
2217 op = (insn >> 9) & 7; in DISAS_INSN()
2504 op = (insn >> 6) & 7; in DISAS_INSN()
2513 dest_ea = ((insn >> 9) & 7) | (op << 3); in DISAS_INSN()
2654 if ((insn & 7) == 0 && semihosting_test(s)) { in DISAS_INSN()
2681 op = (insn >> 6) & 7; in DISAS_INSN()
2821 if ((insn & 7) != 7) { in gen_link()
2945 imm = (insn >> 9) & 7; in DISAS_INSN()
3141 val = (insn >> 9) & 7; in DISAS_INSN()
3342 int count = (insn >> 9) & 7; in shift_im()
3727 tmp = (insn >> 9) & 7; in DISAS_INSN()
3752 tmp = (insn >> 9) & 7; in DISAS_INSN()
3776 tmp = (insn >> 9) & 7; in DISAS_INSN()
3837 tcg_gen_andi_i32(t1, src, 7); in DISAS_INSN()
4253 switch ((insn >> 7) & 3) { in DISAS_INSN()
4464 REG(insn, 0) == 7 && opsize == OS_BYTE in DISAS_INSN()
4781 int mask = (ext >> 10) & 7; in gen_op_fmove_fcr()
4810 case 7: /* Immediate */ in gen_op_fmove_fcr()
4947 switch ((ext >> 13) & 7) { in DISAS_INSN()
4956 cpu_dest = gen_fp_ptr(REG(ext, 7)); in DISAS_INSN()
4962 cpu_src = gen_fp_ptr(REG(ext, 7)); in DISAS_INSN()
4975 case 7: in DISAS_INSN()
4996 cpu_dest = gen_fp_ptr(REG(ext, 7)); in DISAS_INSN()
5231 case 7: /* Ordered !A */ in gen_fcc_cond()
5445 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); in DISAS_INSN()
5584 switch ((insn >> 3) & 7) { in DISAS_INSN()
5863 INSN(sats, 4c80, fff8, CF_ISA_B); in register_m68k_insns()