1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * LoongArch emulation for QEMU - main translation routines.
10 #include "tcg/tcg-op.h"
11 #include "tcg/tcg-op-gvec.h"
12 #include "exec/translation-block.h"
14 #include "exec/helper-proto.h"
15 #include "exec/helper-gen.h"
17 #include "qemu/qemu-print.h"
28 #include "exec/helper-info.c.inc"
46         offs ^= (8 - size);  in vec_reg_offset()
95     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);  in generate_exception()
97     ctx->base.is_jmp = DISAS_NORETURN;  in generate_exception()
102     if (ctx->va32) {  in gen_goto_tb()
106     if (translator_use_goto_tb(&ctx->base, dest)) {  in gen_goto_tb()
109         tcg_gen_exit_tb(ctx->base.tb, n);  in gen_goto_tb()
123     ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;  in loongarch_tr_init_disas_context()
124     ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;  in loongarch_tr_init_disas_context()
125     if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {  in loongarch_tr_init_disas_context()
126         ctx->mem_idx = ctx->plv;  in loongarch_tr_init_disas_context()
128         ctx->mem_idx = MMU_DA_IDX;  in loongarch_tr_init_disas_context()
132     bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;  in loongarch_tr_init_disas_context()
133     ctx->base.max_insns = MIN(ctx->base.max_insns, bound);  in loongarch_tr_init_disas_context()
135     if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LSX)) {  in loongarch_tr_init_disas_context()
136         ctx->vl = LSX_LEN;  in loongarch_tr_init_disas_context()
139     if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LASX)) {  in loongarch_tr_init_disas_context()
140         ctx->vl = LASX_LEN;  in loongarch_tr_init_disas_context()
143     ctx->la64 = is_la64(env);  in loongarch_tr_init_disas_context()
144     ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;  in loongarch_tr_init_disas_context()
146     ctx->zero = tcg_constant_tl(0);  in loongarch_tr_init_disas_context()
148     ctx->cpucfg1 = env->cpucfg[1];  in loongarch_tr_init_disas_context()
149     ctx->cpucfg2 = env->cpucfg[2];  in loongarch_tr_init_disas_context()
160     tcg_gen_insn_start(ctx->base.pc_next);  in loongarch_tr_insn_start()
166  * The $zero register does not have cpu_gpr[0] allocated -- we supply the
176         return ctx->zero;  in gpr_src()
239     if (addend || ctx->va32) {  in make_address_x()
246     if (ctx->va32) {  in make_address_x()
261     if (ctx->va32) {  in make_address_pc()
267 #include "decode-insns.c.inc"
287     ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next);  in loongarch_tr_translate_insn()
289     if (!decode(ctx, ctx->opcode)) {  in loongarch_tr_translate_insn()
292                       ctx->base.pc_next, ctx->opcode);  in loongarch_tr_translate_insn()
296     ctx->base.pc_next += 4;  in loongarch_tr_translate_insn()
298     if (ctx->va32) {  in loongarch_tr_translate_insn()
299         ctx->base.pc_next = (uint32_t)ctx->base.pc_next;  in loongarch_tr_translate_insn()
307     switch (ctx->base.is_jmp) {  in loongarch_tr_tb_stop()
309         tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);  in loongarch_tr_tb_stop()
313         gen_goto_tb(ctx, 0, ctx->base.pc_next);  in loongarch_tr_tb_stop()
318         tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);  in loongarch_tr_tb_stop()