22 #include "helper-tcg.h"
24 #include "hw/core/accel-cpu.h"
26 #include "tcg-cpu.h"
33     CPUX86State *env = &cpu->env;  in x86_cpu_exec_enter()
35     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);  in x86_cpu_exec_enter()
36     env->df = 1 - (2 * ((env->eflags >> 10) & 1));  in x86_cpu_exec_enter()
38     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);  in x86_cpu_exec_enter()
44     CPUX86State *env = &cpu->env;  in x86_cpu_exec_exit()
46     env->eflags = cpu_compute_eflags(env);  in x86_cpu_exec_exit()
56         if (tb->flags & HF_CS64_MASK) {  in x86_cpu_synchronize_from_tb()
57             env->eip = tb->pc;  in x86_cpu_synchronize_from_tb()
59             env->eip = (uint32_t)(tb->pc - tb->cs_base);  in x86_cpu_synchronize_from_tb()
69     CPUX86State *env = &cpu->env;  in x86_restore_state_to_opc()
70     int cc_op = data[1];  in x86_restore_state_to_opc()
75          * data[0] in PC-relative TBs is also a linear address, i.e. an address with  in x86_restore_state_to_opc()
80         uint64_t pc = env->eip + tb->cs_base;  in x86_restore_state_to_opc()
85     if (tb->flags & HF_CS64_MASK) {  in x86_restore_state_to_opc()
86         env->eip = new_pc;  in x86_restore_state_to_opc()
88         env->eip = (uint32_t)(new_pc - tb->cs_base);  in x86_restore_state_to_opc()
92         env->cc_op = cc_op;  in x86_restore_state_to_opc()
100     CPUX86State *env = &cpu->env;  in x86_debug_check_breakpoint()
103     return !(env->eflags & RF_MASK);  in x86_debug_check_breakpoint()
107 #include "hw/core/tcg-cpu-ops.h"
134     cc->tcg_ops = &x86_tcg_ops;  in x86_tcg_cpu_init_ops()
139     cc->init_accel_cpu = x86_tcg_cpu_init_ops;  in x86_tcg_cpu_class_init()
144 #define XO(bit, field) \  in x86_tcg_cpu_xsave_init()  macro
147     XO(XSTATE_FP_BIT, legacy);  in x86_tcg_cpu_xsave_init()
148     XO(XSTATE_SSE_BIT, legacy);  in x86_tcg_cpu_xsave_init()
149     XO(XSTATE_YMM_BIT, avx_state);  in x86_tcg_cpu_xsave_init()
150     XO(XSTATE_BNDREGS_BIT, bndreg_state);  in x86_tcg_cpu_xsave_init()
151     XO(XSTATE_BNDCSR_BIT, bndcsr_state);  in x86_tcg_cpu_xsave_init()
152     XO(XSTATE_OPMASK_BIT, opmask_state);  in x86_tcg_cpu_xsave_init()
153     XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state);  in x86_tcg_cpu_xsave_init()
154     XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state);  in x86_tcg_cpu_xsave_init()
155     XO(XSTATE_PKRU_BIT, pkru_state);  in x86_tcg_cpu_xsave_init()
157 #undef XO  in x86_tcg_cpu_xsave_init()
161  * TCG-specific defaults that override cpudef models when using TCG.
174     if (xcc->model) {  in x86_tcg_cpu_instance_init()
187     acc->cpu_target_realize = tcg_cpu_realizefn;  in x86_tcg_cpu_accel_class_init()
190     acc->cpu_class_init = x86_tcg_cpu_class_init;  in x86_tcg_cpu_accel_class_init()
191     acc->cpu_instance_init = x86_tcg_cpu_instance_init;  in x86_tcg_cpu_accel_class_init()