80     if (hv_vcpu_write_fpstate(cs->accel->fd, xsave, xsave_len)) {  in hvf_put_xsave()
90     wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);  in hvf_put_segments()
91     wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE, env->idt.base);  in hvf_put_segments()
93     wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);  in hvf_put_segments()
94     wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);  in hvf_put_segments()
96     /* wvmcs(cs->accel->fd, VMCS_GUEST_CR2, env->cr[2]); */  in hvf_put_segments()
97     wvmcs(cs->accel->fd, VMCS_GUEST_CR3, env->cr[3]);  in hvf_put_segments()
99     wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, env->efer);  in hvf_put_segments()
101     macvm_set_cr4(cs->accel->fd, env->cr[4]);  in hvf_put_segments()
102     macvm_set_cr0(cs->accel->fd, env->cr[0]);  in hvf_put_segments()
133     hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_CS,  in hvf_put_msrs()
135     hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_ESP,  in hvf_put_msrs()
137     hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_EIP,  in hvf_put_msrs()
140     hv_vcpu_write_msr(cs->accel->fd, MSR_STAR, env->star);  in hvf_put_msrs()
143     hv_vcpu_write_msr(cs->accel->fd, MSR_CSTAR, env->cstar);  in hvf_put_msrs()
144     hv_vcpu_write_msr(cs->accel->fd, MSR_KERNELGSBASE, env->kernelgsbase);  in hvf_put_msrs()
145     hv_vcpu_write_msr(cs->accel->fd, MSR_FMASK, env->fmask);  in hvf_put_msrs()
146     hv_vcpu_write_msr(cs->accel->fd, MSR_LSTAR, env->lstar);  in hvf_put_msrs()
149     hv_vcpu_write_msr(cs->accel->fd, MSR_GSBASE, env->segs[R_GS].base);  in hvf_put_msrs()
150     hv_vcpu_write_msr(cs->accel->fd, MSR_FSBASE, env->segs[R_FS].base);  in hvf_put_msrs()
159     if (hv_vcpu_read_fpstate(cs->accel->fd, xsave, xsave_len)) {  in hvf_get_xsave()
198     env->idt.limit = rvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT);  in hvf_get_segments()
199     env->idt.base = rvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE);  in hvf_get_segments()
200     env->gdt.limit = rvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT);  in hvf_get_segments()
201     env->gdt.base = rvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE);  in hvf_get_segments()
203     env->cr[0] = rvmcs(cs->accel->fd, VMCS_GUEST_CR0);  in hvf_get_segments()
205     env->cr[3] = rvmcs(cs->accel->fd, VMCS_GUEST_CR3);  in hvf_get_segments()
206     env->cr[4] = rvmcs(cs->accel->fd, VMCS_GUEST_CR4);  in hvf_get_segments()
208     env->efer = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);  in hvf_get_segments()
216     hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_CS, &tmp);  in hvf_get_msrs()
219     hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_ESP, &tmp);  in hvf_get_msrs()
222     hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_EIP, &tmp);  in hvf_get_msrs()
225     hv_vcpu_read_msr(cs->accel->fd, MSR_STAR, &env->star);  in hvf_get_msrs()
228     hv_vcpu_read_msr(cs->accel->fd, MSR_CSTAR, &env->cstar);  in hvf_get_msrs()
229     hv_vcpu_read_msr(cs->accel->fd, MSR_KERNELGSBASE, &env->kernelgsbase);  in hvf_get_msrs()
230     hv_vcpu_read_msr(cs->accel->fd, MSR_FMASK, &env->fmask);  in hvf_get_msrs()
231     hv_vcpu_read_msr(cs->accel->fd, MSR_LSTAR, &env->lstar);  in hvf_get_msrs()
234     hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_APICBASE, &tmp);  in hvf_get_msrs()
236     env->tsc = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);  in hvf_get_msrs()
244     wreg(cs->accel->fd, HV_X86_RAX, env->regs[R_EAX]);  in hvf_put_registers()
245     wreg(cs->accel->fd, HV_X86_RBX, env->regs[R_EBX]);  in hvf_put_registers()
246     wreg(cs->accel->fd, HV_X86_RCX, env->regs[R_ECX]);  in hvf_put_registers()
247     wreg(cs->accel->fd, HV_X86_RDX, env->regs[R_EDX]);  in hvf_put_registers()
248     wreg(cs->accel->fd, HV_X86_RBP, env->regs[R_EBP]);  in hvf_put_registers()
249     wreg(cs->accel->fd, HV_X86_RSP, env->regs[R_ESP]);  in hvf_put_registers()
250     wreg(cs->accel->fd, HV_X86_RSI, env->regs[R_ESI]);  in hvf_put_registers()
251     wreg(cs->accel->fd, HV_X86_RDI, env->regs[R_EDI]);  in hvf_put_registers()
252     wreg(cs->accel->fd, HV_X86_R8, env->regs[8]);  in hvf_put_registers()
253     wreg(cs->accel->fd, HV_X86_R9, env->regs[9]);  in hvf_put_registers()
254     wreg(cs->accel->fd, HV_X86_R10, env->regs[10]);  in hvf_put_registers()
255     wreg(cs->accel->fd, HV_X86_R11, env->regs[11]);  in hvf_put_registers()
256     wreg(cs->accel->fd, HV_X86_R12, env->regs[12]);  in hvf_put_registers()
257     wreg(cs->accel->fd, HV_X86_R13, env->regs[13]);  in hvf_put_registers()
258     wreg(cs->accel->fd, HV_X86_R14, env->regs[14]);  in hvf_put_registers()
259     wreg(cs->accel->fd, HV_X86_R15, env->regs[15]);  in hvf_put_registers()
260     wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);  in hvf_put_registers()
261     wreg(cs->accel->fd, HV_X86_RIP, env->eip);  in hvf_put_registers()
263     wreg(cs->accel->fd, HV_X86_XCR0, env->xcr0);  in hvf_put_registers()
271     wreg(cs->accel->fd, HV_X86_DR0, env->dr[0]);  in hvf_put_registers()
272     wreg(cs->accel->fd, HV_X86_DR1, env->dr[1]);  in hvf_put_registers()
273     wreg(cs->accel->fd, HV_X86_DR2, env->dr[2]);  in hvf_put_registers()
274     wreg(cs->accel->fd, HV_X86_DR3, env->dr[3]);  in hvf_put_registers()
275     wreg(cs->accel->fd, HV_X86_DR4, env->dr[4]);  in hvf_put_registers()
276     wreg(cs->accel->fd, HV_X86_DR5, env->dr[5]);  in hvf_put_registers()
277     wreg(cs->accel->fd, HV_X86_DR6, env->dr[6]);  in hvf_put_registers()
278     wreg(cs->accel->fd, HV_X86_DR7, env->dr[7]);  in hvf_put_registers()
288     env->regs[R_EAX] = rreg(cs->accel->fd, HV_X86_RAX);  in hvf_get_registers()
289     env->regs[R_EBX] = rreg(cs->accel->fd, HV_X86_RBX);  in hvf_get_registers()
290     env->regs[R_ECX] = rreg(cs->accel->fd, HV_X86_RCX);  in hvf_get_registers()
291     env->regs[R_EDX] = rreg(cs->accel->fd, HV_X86_RDX);  in hvf_get_registers()
292     env->regs[R_EBP] = rreg(cs->accel->fd, HV_X86_RBP);  in hvf_get_registers()
293     env->regs[R_ESP] = rreg(cs->accel->fd, HV_X86_RSP);  in hvf_get_registers()
294     env->regs[R_ESI] = rreg(cs->accel->fd, HV_X86_RSI);  in hvf_get_registers()
295     env->regs[R_EDI] = rreg(cs->accel->fd, HV_X86_RDI);  in hvf_get_registers()
296     env->regs[8] = rreg(cs->accel->fd, HV_X86_R8);  in hvf_get_registers()
297     env->regs[9] = rreg(cs->accel->fd, HV_X86_R9);  in hvf_get_registers()
298     env->regs[10] = rreg(cs->accel->fd, HV_X86_R10);  in hvf_get_registers()
299     env->regs[11] = rreg(cs->accel->fd, HV_X86_R11);  in hvf_get_registers()
300     env->regs[12] = rreg(cs->accel->fd, HV_X86_R12);  in hvf_get_registers()
301     env->regs[13] = rreg(cs->accel->fd, HV_X86_R13);  in hvf_get_registers()
302     env->regs[14] = rreg(cs->accel->fd, HV_X86_R14);  in hvf_get_registers()
303     env->regs[15] = rreg(cs->accel->fd, HV_X86_R15);  in hvf_get_registers()
305     env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);  in hvf_get_registers()
306     env->eip = rreg(cs->accel->fd, HV_X86_RIP);  in hvf_get_registers()
309     env->xcr0 = rreg(cs->accel->fd, HV_X86_XCR0);  in hvf_get_registers()
314     env->dr[0] = rreg(cs->accel->fd, HV_X86_DR0);  in hvf_get_registers()
315     env->dr[1] = rreg(cs->accel->fd, HV_X86_DR1);  in hvf_get_registers()
316     env->dr[2] = rreg(cs->accel->fd, HV_X86_DR2);  in hvf_get_registers()
317     env->dr[3] = rreg(cs->accel->fd, HV_X86_DR3);  in hvf_get_registers()
318     env->dr[4] = rreg(cs->accel->fd, HV_X86_DR4);  in hvf_get_registers()
319     env->dr[5] = rreg(cs->accel->fd, HV_X86_DR5);  in hvf_get_registers()
320     env->dr[6] = rreg(cs->accel->fd, HV_X86_DR6);  in hvf_get_registers()
321     env->dr[7] = rreg(cs->accel->fd, HV_X86_DR7);  in hvf_get_registers()
330      val = rvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS);  in vmx_set_int_window_exiting()
331      wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val |  in vmx_set_int_window_exiting()
338      val = rvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS);  in vmx_clear_int_window_exiting()
339      wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val &  in vmx_clear_int_window_exiting()
375         uint64_t reason = rvmcs(cs->accel->fd, VMCS_EXIT_REASON);  in hvf_inject_interrupts()
384                 wvmcs(cs->accel->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);  in hvf_inject_interrupts()
388                 wvmcs(cs->accel->fd, VMCS_ENTRY_EXCEPTION_ERROR,  in hvf_inject_interrupts()
394             wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info);  in hvf_inject_interrupts()
402             wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info);  in hvf_inject_interrupts()
414             wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line |  in hvf_inject_interrupts()
430     if (!cs->accel->dirty) {  in hvf_process_events()
432         env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);  in hvf_process_events()