Lines Matching +full:0 +full:x259
50 R_EAX = 0,
67 R_AL = 0,
78 R_ES = 0,
107 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
117 #define CC_C 0x0001
118 #define CC_P 0x0004
119 #define CC_A 0x0010
120 #define CC_Z 0x0040
121 #define CC_S 0x0080
122 #define CC_O 0x0800
128 #define TF_MASK 0x00000100
129 #define IF_MASK 0x00000200
130 #define DF_MASK 0x00000400
131 #define IOPL_MASK 0x00003000
132 #define NT_MASK 0x00004000
133 #define RF_MASK 0x00010000
134 #define VM_MASK 0x00020000
135 #define AC_MASK 0x00040000
136 #define VIF_MASK 0x00080000
137 #define VIP_MASK 0x00100000
138 #define ID_MASK 0x00200000
145 #define HF_CPL_SHIFT 0
151 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
205 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
212 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
225 #define CR0_PE_SHIFT 0
228 #define CR0_PE_MASK (1U << 0)
240 #define CR4_VME_MASK (1U << 0)
268 #define CR4_FRED_MASK 0
284 #define DR6_FIXED_1 0xffff0ff0
289 #define DR7_FIXED_1 0x00000400
290 #define DR7_GLOBAL_BP_MASK 0xaa
291 #define DR7_LOCAL_BP_MASK 0x55
293 #define DR7_TYPE_BP_INST 0x0
294 #define DR7_TYPE_DATA_WR 0x1
295 #define DR7_TYPE_IO_RW 0x2
296 #define DR7_TYPE_DATA_RW 0x3
298 #define DR_RESERVED_MASK 0xffffffff00000000ULL
300 #define PG_PRESENT_BIT 0
323 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
324 #define PG_HI_USER_MASK 0x7ff0000000000000LL
330 #define PG_ERROR_P_MASK 0x01
332 #define PG_ERROR_U_MASK 0x04
333 #define PG_ERROR_RSVD_MASK 0x08
334 #define PG_ERROR_I_D_MASK 0x10
335 #define PG_ERROR_PK_MASK 0x20
337 #define PG_MODE_PAE (1 << 0)
342 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
358 #define MCG_CAP_BANKS_MASK 0xff
360 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
365 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
380 #define MCM_ADDR_SEGOFF 0 /* segment offset */
386 #define MSR_IA32_TSC 0x10
387 #define MSR_IA32_APICBASE 0x1b
391 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
396 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
397 #define MSR_TSC_ADJUST 0x0000003b
398 #define MSR_IA32_SPEC_CTRL 0x48
399 #define MSR_VIRT_SSBD 0xc001011f
400 #define MSR_IA32_PRED_CMD 0x49
401 #define MSR_IA32_UCODE_REV 0x8b
402 #define MSR_IA32_CORE_CAPABILITY 0xcf
404 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
407 #define MSR_IA32_PERF_CAPABILITIES 0x345
408 #define PERF_CAP_LBR_FMT 0x3f
410 #define MSR_IA32_TSX_CTRL 0x122
411 #define MSR_IA32_TSCDEADLINE 0x6e0
412 #define MSR_IA32_PKRS 0x6e1
413 #define MSR_RAPL_POWER_UNIT 0x00000606
414 #define MSR_PKG_POWER_LIMIT 0x00000610
415 #define MSR_PKG_ENERGY_STATUS 0x00000611
416 #define MSR_PKG_POWER_INFO 0x00000614
417 #define MSR_ARCH_LBR_CTL 0x000014ce
418 #define MSR_ARCH_LBR_DEPTH 0x000014cf
419 #define MSR_ARCH_LBR_FROM_0 0x00001500
420 #define MSR_ARCH_LBR_TO_0 0x00001600
421 #define MSR_ARCH_LBR_INFO_0 0x00001200
423 #define FEATURE_CONTROL_LOCKED (1<<0)
430 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
431 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
432 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
433 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
435 #define MSR_P6_PERFCTR0 0xc1
437 #define MSR_IA32_SMBASE 0x9e
438 #define MSR_SMI_COUNT 0x34
439 #define MSR_CORE_THREAD_COUNT 0x35
440 #define MSR_MTRRcap 0xfe
445 #define MSR_IA32_SYSENTER_CS 0x174
446 #define MSR_IA32_SYSENTER_ESP 0x175
447 #define MSR_IA32_SYSENTER_EIP 0x176
449 #define MSR_MCG_CAP 0x179
450 #define MSR_MCG_STATUS 0x17a
451 #define MSR_MCG_CTL 0x17b
452 #define MSR_MCG_EXT_CTL 0x4d0
454 #define MSR_P6_EVNTSEL0 0x186
456 #define MSR_IA32_PERF_STATUS 0x198
458 #define MSR_IA32_MISC_ENABLE 0x1a0
463 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
464 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
466 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
468 #define MSR_MTRRfix64K_00000 0x250
469 #define MSR_MTRRfix16K_80000 0x258
470 #define MSR_MTRRfix16K_A0000 0x259
471 #define MSR_MTRRfix4K_C0000 0x268
472 #define MSR_MTRRfix4K_C8000 0x269
473 #define MSR_MTRRfix4K_D0000 0x26a
474 #define MSR_MTRRfix4K_D8000 0x26b
475 #define MSR_MTRRfix4K_E0000 0x26c
476 #define MSR_MTRRfix4K_E8000 0x26d
477 #define MSR_MTRRfix4K_F0000 0x26e
478 #define MSR_MTRRfix4K_F8000 0x26f
480 #define MSR_PAT 0x277
482 #define MSR_MTRRdefType 0x2ff
484 #define MSR_CORE_PERF_FIXED_CTR0 0x309
485 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
486 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
487 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
488 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
489 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
490 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
492 #define MSR_MC0_CTL 0x400
493 #define MSR_MC0_STATUS 0x401
494 #define MSR_MC0_ADDR 0x402
495 #define MSR_MC0_MISC 0x403
497 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
498 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
499 #define MSR_IA32_RTIT_CTL 0x570
500 #define MSR_IA32_RTIT_STATUS 0x571
501 #define MSR_IA32_RTIT_CR3_MATCH 0x572
502 #define MSR_IA32_RTIT_ADDR0_A 0x580
503 #define MSR_IA32_RTIT_ADDR0_B 0x581
504 #define MSR_IA32_RTIT_ADDR1_A 0x582
505 #define MSR_IA32_RTIT_ADDR1_B 0x583
506 #define MSR_IA32_RTIT_ADDR2_A 0x584
507 #define MSR_IA32_RTIT_ADDR2_B 0x585
508 #define MSR_IA32_RTIT_ADDR3_A 0x586
509 #define MSR_IA32_RTIT_ADDR3_B 0x587
512 #define MSR_EFER 0xc0000080
514 #define MSR_EFER_SCE (1 << 0)
526 #define MSR_STAR 0xc0000081
527 #define MSR_LSTAR 0xc0000082
528 #define MSR_CSTAR 0xc0000083
529 #define MSR_FMASK 0xc0000084
530 #define MSR_FSBASE 0xc0000100
531 #define MSR_GSBASE 0xc0000101
532 #define MSR_KERNELGSBASE 0xc0000102
533 #define MSR_TSC_AUX 0xc0000103
534 #define MSR_AMD64_TSC_RATIO 0xc0000104
536 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
538 #define MSR_K7_HWCR 0xc0010015
540 #define MSR_VM_HSAVE_PA 0xc0010117
542 #define MSR_IA32_XFD 0x000001c4
543 #define MSR_IA32_XFD_ERR 0x000001c5
546 #define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */
547 #define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */
548 #define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */
549 #define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 regular stack pointer */
550 #define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception stack levels */
551 #define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in r…
552 #define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 shadow stack pointer in r…
553 #define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in r…
554 #define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack lev…
556 #define MSR_IA32_BNDCFGS 0x00000d90
557 #define MSR_IA32_XSS 0x00000da0
558 #define MSR_IA32_UMWAIT_CONTROL 0xe1
560 #define MSR_IA32_VMX_BASIC 0x00000480
561 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
562 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
563 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
564 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
565 #define MSR_IA32_VMX_MISC 0x00000485
566 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
567 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
568 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
569 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
570 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
571 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
572 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
573 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
574 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
575 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
576 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
577 #define MSR_IA32_VMX_VMFUNC 0x00000491
579 #define MSR_APIC_START 0x00000800
580 #define MSR_APIC_END 0x000008ff
582 #define XSTATE_FP_BIT 0
629 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
630 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
631 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
645 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
647 FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
648 FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
662 FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
663 FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
664 FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
665 FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */
666 FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
669 FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
677 #define CPUID_FP87 (1U << 0)
708 #define CPUID_EXT_SSE3 (1U << 0)
739 #define CPUID_EXT2_FPU (1U << 0)
779 #define CPUID_EXT3_LAHF_LM (1U << 0)
802 #define CPUID_SVM_NPT (1U << 0)
819 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
1010 #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
1014 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
1035 #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0)
1060 #define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0)
1062 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
1069 /* CPUID[0x80000007].EDX flags: */
1074 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
1075 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
1076 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
1079 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
1080 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
1081 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
1096 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
1098 /* CPUID[0xB].ECX level types */
1099 #define CPUID_B_ECX_TOPO_LEVEL_INVALID 0
1103 /* COUID[0x1F].ECX level types */
1111 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1129 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
1130 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
1131 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
1138 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1143 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1147 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1165 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1169 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1170 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1171 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1172 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1173 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1174 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1175 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1176 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1177 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1178 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1179 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1180 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1181 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1182 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1183 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1184 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1185 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1186 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1187 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1188 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1189 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1191 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1192 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1193 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1194 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1195 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1196 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1197 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1198 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1199 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1200 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1201 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1202 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1203 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1204 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1205 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1206 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1207 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1208 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1209 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1210 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1211 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000
1213 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1214 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1215 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1216 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1217 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1219 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1220 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1221 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1222 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1223 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1224 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1225 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1226 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1227 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1228 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1229 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1230 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1231 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1232 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1234 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1235 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1236 #define VMX_VM_ENTRY_SMM 0x00000400
1237 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1238 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1239 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1240 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1241 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1242 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1243 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1244 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1247 #define HYPERV_FEAT_RELAXED 0
1270 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1273 #define EXCP00_DIVZ 0
1292 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1293 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1294 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1318 CC_OP_EFLAGS = 0, /* all cc are explicitly computed, CC_SRC = flags */
1325 CC_OP_MULB = 4, /* modify all flags, C, O = (CC_SRC != 0) */
1375 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1380 CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
1534 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1537 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1639 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1640 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1641 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1642 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1643 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1644 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1645 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1646 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1647 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1648 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1685 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1687 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1691 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1701 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1706 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1718 * CPUID[0x8000001D].EAX[bits 25:14].
1749 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1779 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1925 }; /* break/watchpoints for dr[0..3] */
2110 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
2167 * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2359 } else if (!(env->cr[0] & CR0_PE_MASK) || in cpu_x86_load_seg_cache()
2371 env->segs[R_SS].base) != 0) << in cpu_x86_load_seg_cache()
2385 env->eip = 0; in cpu_x86_load_seg_cache_sipi()
2390 cs->halted = 0; in cpu_x86_load_seg_cache_sipi()
2486 #define MMU_KSMAP64_IDX 0
2540 *cs_base = 0; in cpu_get_tb_cpu_state()
2570 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); in cpu_get_mem_attrs()
2673 #define CPU_VERSION_LEGACY 0
2687 #define APIC_DEFAULT_ADDRESS 0xfee00000
2688 #define APIC_SPACE_SIZE 0x100000