Lines Matching +full:cross +full:- +full:win64 +full:- +full:system
23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
27 #include "exec/translation-block.h"
28 #include "system/hvf.h"
29 #include "hvf/hvf-i386.h"
34 #include "qemu/error-report.h"
35 #include "qapi/qapi-visit-machine.h"
36 #include "standard-headers/asm-x86/kvm_para.h"
37 #include "hw/qdev-properties.h"
41 #include "confidential-guest.h"
42 #include "system/reset.h"
43 #include "qapi/qapi-commands-machine.h"
44 #include "system/address-spaces.h"
46 #include "hw/i386/sgx-epc.h"
48 #include "system/qtest.h"
49 #include "tcg/tcg-cpu.h"
52 #include "cpu-internal.h"
134 * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.
135 * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
232 assert(cache->size > 0); in cpuid2_cache_descriptor()
233 assert(cache->level > 0); in cpuid2_cache_descriptor()
234 assert(cache->line_size > 0); in cpuid2_cache_descriptor()
235 assert(cache->associativity > 0); in cpuid2_cache_descriptor()
238 if (d->level == cache->level && d->type == cache->type && in cpuid2_cache_descriptor()
239 d->size == cache->size && d->line_size == cache->line_size && in cpuid2_cache_descriptor()
240 d->associativity == cache->associativity) { in cpuid2_cache_descriptor()
257 CPUX86State *env = &cpu->env; in encode_cache_cpuid2()
264 l1d = cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); in encode_cache_cpuid2()
265 l1i = cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); in encode_cache_cpuid2()
266 l2 = cpuid2_cache_descriptor(caches->l2_cache, &unmatched); in encode_cache_cpuid2()
267 l3 = cpuid2_cache_descriptor(caches->l3_cache, &unmatched); in encode_cache_cpuid2()
269 if (!cpu->consistent_cache || in encode_cache_cpuid2()
270 (env->cpuid_min_level < 0x4 && !unmatched)) { in encode_cache_cpuid2()
275 if (cpu->enable_l3_cache) { in encode_cache_cpuid2()
333 return num_ids - 1; in max_thread_ids_for_cache()
338 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - in max_core_ids_in_package()
340 return num_cores - 1; in max_core_ids_in_package()
349 assert(cache->size == cache->line_size * cache->associativity * in encode_cache_cpuid4()
350 cache->partitions * cache->sets); in encode_cache_cpuid4()
353 * The following fields have bit-width limitations, so consider the in encode_cache_cpuid4()
355 * Bits 25-14: maximum 4095. in encode_cache_cpuid4()
356 * Bits 31-26: maximum 63. in encode_cache_cpuid4()
358 *eax = CACHE_TYPE(cache->type) | in encode_cache_cpuid4()
359 CACHE_LEVEL(cache->level) | in encode_cache_cpuid4()
360 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | in encode_cache_cpuid4()
362 (MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14); in encode_cache_cpuid4()
364 assert(cache->line_size > 0); in encode_cache_cpuid4()
365 assert(cache->partitions > 0); in encode_cache_cpuid4()
366 assert(cache->associativity > 0); in encode_cache_cpuid4()
367 /* We don't implement fully-associative caches */ in encode_cache_cpuid4()
368 assert(cache->associativity < cache->sets); in encode_cache_cpuid4()
369 *ebx = (cache->line_size - 1) | in encode_cache_cpuid4()
370 ((cache->partitions - 1) << 12) | in encode_cache_cpuid4()
371 ((cache->associativity - 1) << 22); in encode_cache_cpuid4()
373 assert(cache->sets > 0); in encode_cache_cpuid4()
374 *ecx = cache->sets - 1; in encode_cache_cpuid4()
376 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid4()
377 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid4()
378 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid4()
388 return topo_info->threads_per_core; in num_threads_by_topo_level()
459 level = find_next_bit(env->avail_cpu_topo, in encode_topo_cpuid1f()
480 next_level = find_next_bit(env->avail_cpu_topo, in encode_topo_cpuid1f()
490 /* The count (bits 15-00) doesn't need to be reliable. */ in encode_topo_cpuid1f()
493 *edx = cpu->apic_id; in encode_topo_cpuid1f()
501 assert(cache->size % 1024 == 0); in encode_cache_cpuid80000005()
502 assert(cache->associativity > 0); in encode_cache_cpuid80000005()
503 assert(cache->line_size > 0); in encode_cache_cpuid80000005()
504 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | in encode_cache_cpuid80000005()
505 (cache->lines_per_tag << 8) | (cache->line_size); in encode_cache_cpuid80000005()
532 assert(l2->size % 1024 == 0); in encode_cache_cpuid80000006()
533 assert(l2->associativity > 0); in encode_cache_cpuid80000006()
534 assert(l2->line_size > 0); in encode_cache_cpuid80000006()
535 *ecx = ((l2->size / 1024) << 16) | in encode_cache_cpuid80000006()
536 (X86_ENC_ASSOC(l2->associativity) << 12) | in encode_cache_cpuid80000006()
537 (l2->lines_per_tag << 8) | (l2->line_size); in encode_cache_cpuid80000006()
541 assert(l3->size % (512 * 1024) == 0); in encode_cache_cpuid80000006()
542 assert(l3->associativity > 0); in encode_cache_cpuid80000006()
543 assert(l3->line_size > 0); in encode_cache_cpuid80000006()
544 *edx = ((l3->size / (512 * 1024)) << 18) | in encode_cache_cpuid80000006()
545 (X86_ENC_ASSOC(l3->associativity) << 12) | in encode_cache_cpuid80000006()
546 (l3->lines_per_tag << 8) | (l3->line_size); in encode_cache_cpuid80000006()
558 assert(cache->size == cache->line_size * cache->associativity * in encode_cache_cpuid8000001d()
559 cache->partitions * cache->sets); in encode_cache_cpuid8000001d()
561 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | in encode_cache_cpuid8000001d()
562 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); in encode_cache_cpuid8000001d()
563 /* Bits 25:14 - NumSharingCache: maximum 4095. */ in encode_cache_cpuid8000001d()
564 *eax |= MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14; in encode_cache_cpuid8000001d()
566 assert(cache->line_size > 0); in encode_cache_cpuid8000001d()
567 assert(cache->partitions > 0); in encode_cache_cpuid8000001d()
568 assert(cache->associativity > 0); in encode_cache_cpuid8000001d()
569 /* We don't implement fully-associative caches */ in encode_cache_cpuid8000001d()
570 assert(cache->associativity < cache->sets); in encode_cache_cpuid8000001d()
571 *ebx = (cache->line_size - 1) | in encode_cache_cpuid8000001d()
572 ((cache->partitions - 1) << 12) | in encode_cache_cpuid8000001d()
573 ((cache->associativity - 1) << 22); in encode_cache_cpuid8000001d()
575 assert(cache->sets > 0); in encode_cache_cpuid8000001d()
576 *ecx = cache->sets - 1; in encode_cache_cpuid8000001d()
578 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid8000001d()
579 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid8000001d()
580 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid8000001d()
590 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); in encode_topo_cpuid8000001e()
592 *eax = cpu->apic_id; in encode_topo_cpuid8000001e()
596 * Read-only. Reset: 0000_XXXXh. in encode_topo_cpuid8000001e()
601 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
603 * 7:0 CoreId: core ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
608 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); in encode_topo_cpuid8000001e()
612 * Read-only. Reset: 0000_0XXXh. in encode_topo_cpuid8000001e()
616 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. in encode_topo_cpuid8000001e()
620 * 7h-1h Reserved. in encode_topo_cpuid8000001e()
621 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
629 if (cpu->legacy_multi_node) { in encode_topo_cpuid8000001e()
630 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | in encode_topo_cpuid8000001e()
631 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); in encode_topo_cpuid8000001e()
633 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; in encode_topo_cpuid8000001e()
839 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
842 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
852 * bit[02]: Support Single-Range Output scheme;
906 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
911 * Kernel-only features that can be shown to usermode programs even if
912 * they aren't actually supported by TCG, because qemu-user only runs
913 * in CPL=3; remove them if they are ever implemented for system emulation.
943 * in usermode or by 32-bit programs. Those are added to supported
944 * TCG features unconditionally in user-mode emulation mode. This may
948 * Even for long mode, qemu-i386 is not running "a userspace program on a
949 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
950 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit
956 /* FIXME: Long mode not yet supported for i386 bsd-user */
1084 "ds-cpl", "vmx", "smx", "est",
1089 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
1109 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
1118 "lahf-lm", "cmp-legacy", "svm", "extapic",
1122 "fma4", "tce", NULL, "nodeid-msr",
1123 NULL, "tbm", "topoext", "perfctr-core",
1124 "perfctr-nb", NULL, NULL, NULL,
1131 * "-cpu host", as it requires consistent cache topology info
1139 NULL, NULL, "xstore", "xstore-en",
1140 NULL, NULL, "xcrypt", "xcrypt-en",
1141 "ace2", "ace2-en", "phe", "phe-en",
1142 "pmm", "pmm-en", NULL, NULL,
1154 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
1155 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
1156 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi",
1157 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
1160 "kvmclock-stable-bit", NULL, NULL, NULL,
1169 "kvm-hint-dedicated", NULL, NULL, NULL,
1181 * KVM hints aren't auto-enabled by -cpu host, they need to be
1182 * explicitly enabled in the command-line.
1189 "npt", "lbrv", "svm-lock", "nrip-save",
1190 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1191 NULL, NULL, "pause-filter", NULL,
1192 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
1196 "svme-addr-chk", NULL, NULL, NULL,
1204 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
1205 "hle", "avx2", "fdp-excptn-only", "smep",
1207 NULL, "zero-fcs-fds", "mpx", NULL,
1210 "clwb", "intel-pt", "avx512pf", "avx512er",
1211 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1226 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1229 "bus-lock-detect", "cldemote", NULL, "movdiri",
1242 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1244 "avx512-vp2intersect", NULL, "md-clear", NULL,
1246 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
1247 NULL, NULL, "amx-bf16", "avx512-fp16",
1248 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
1249 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
1262 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
1266 NULL, "amx-fp16", NULL, "avx-ifma",
1281 NULL, "msr-imm", NULL, NULL,
1300 "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
1301 "amx-complex", NULL, "avx-vnni-int16", NULL,
1318 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
1319 "bhi-ctrl", "mcdt-no", NULL, NULL,
1337 [16] = "avx10-128",
1338 [17] = "avx10-256",
1339 [18] = "avx10-512",
1367 "overflow-recov", "succor", NULL, NULL,
1386 "ibpb", NULL, "ibrs", "amd-stibp",
1387 NULL, "stibp-always-on", NULL, NULL,
1389 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1390 "amd-psfd", NULL, NULL, NULL,
1399 "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL,
1400 NULL, NULL, "null-sel-clr-base", NULL,
1401 "auto-ibrs", NULL, NULL, NULL,
1406 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
1421 "perfmon-v2", NULL, NULL, NULL,
1524 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1525 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1526 "taa-no", NULL, NULL, NULL,
1527 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
1528 NULL, "fb-clear", NULL, NULL,
1529 "bhi-no", NULL, NULL, NULL,
1530 "pbrsb-no", NULL, "gds-no", "rfds-no",
1531 "rfds-clear", NULL, NULL, NULL,
1539 NULL, NULL, "its-no", NULL,
1545 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
1547 > on any user-mode operation, and warnings about unsupported
1556 NULL, "split-lock-detect", NULL, NULL,
1574 NULL, "full-width-write", NULL, NULL,
1588 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1589 NULL, NULL, NULL, "vmx-hlt-exit",
1590 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1591 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1592 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1593 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1594 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1595 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1605 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1606 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1607 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1608 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1609 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1610 "vmx-xsaves", NULL, NULL, NULL,
1611 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
1622 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1623 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1643 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1645 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1646 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1647 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1648 "vmx-exit-save-efer", "vmx-exit-load-efer",
1649 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1650 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1651 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls",
1661 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1663 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1664 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1665 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1666 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred",
1679 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1680 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1685 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1695 "vmx-ept-execonly", NULL, NULL, NULL,
1696 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1699 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1700 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1701 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1703 "vmx-invvpid", NULL, NULL, NULL,
1705 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1706 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1721 [54] = "vmx-ins-outs",
1722 [55] = "vmx-true-ctls",
1723 [56] = "vmx-any-errcode",
1724 [58] = "vmx-nested-exception",
1729 /* Just to be safe - we don't support setting the MSEG version field. */
1736 [0] = "vmx-eptp-switching",
1753 NULL, NULL, NULL, "intel-pt-lip",
1768 NULL, NULL, NULL, "sgx-edeccssa",
1786 "sgx-exinfo" , NULL, NULL, NULL,
1806 NULL, "sgx-debug", "sgx-mode64", NULL,
1807 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1808 NULL, NULL, "sgx-aex-notify", NULL,
1831 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && in is_feature_word_cpuid()
1832 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && in is_feature_word_cpuid()
1833 wi->cpuid.reg == reg) { in is_feature_word_cpuid()
2060 offset = compacted ? ret : esa->offset; in xsave_area_size()
2061 ret = MAX(ret, offset + esa->size); in xsave_area_size()
2074 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | in x86_cpu_xsave_xcr0_components()
2075 cpu->env.features[FEAT_XSAVE_XCR0_LO]; in x86_cpu_xsave_xcr0_components()
2078 /* Return name of 32-bit register, from a R_* constant */
2089 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | in x86_cpu_xsave_xss_components()
2090 cpu->env.features[FEAT_XSAVE_XSS_LO]; in x86_cpu_xsave_xss_components()
2100 CPUX86State *env = &cpu->env; in x86_cpu_get_migratable_flags()
2109 if ((wi->migratable_flags & f) || in x86_cpu_get_migratable_flags()
2110 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { in x86_cpu_get_migratable_flags()
2115 /* when tsc-khz is set explicitly, invtsc is migratable */ in x86_cpu_get_migratable_flags()
2116 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { in x86_cpu_get_migratable_flags()
2193 /* vendor is zero-terminated, 12 character ASCII string */
2220 * This matters only for "-cpu help" and query-cpu-definitions
2230 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); in x86_cpu_versioned_model_name()
2242 return def->versions ?: default_version_list; in x86_cpu_def_get_versions()
3268 * Dual-monitor support (all processors)
3270 * Deactivate dual-monitor treatment
3271 * Number of CR3-target values
3273 * Wait-for-SIPI activity state
3274 * PAUSE-loop exiting (Westmere and newer)
3275 * EPT-violation #VE (Broadwell and newer)
3277 * Conceal non-root operation from PT
3281 * Mode-based execute control (XS/XU)
3288 * Advanced VM-exit information for EPT violations
3289 * Sub-page write permissions
3344 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
3471 .model_id = "Common 32-bit KVM processor"
3748 .alias = "Nehalem-IBRS",
3750 { "spec-ctrl", "on" },
3751 { "model-id",
3824 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
3829 .alias = "Westmere-IBRS",
3831 { "spec-ctrl", "on" },
3832 { "model-id",
3915 .alias = "SandyBridge-IBRS",
3917 { "spec-ctrl", "on" },
3918 { "model-id",
4002 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
4007 .alias = "IvyBridge-IBRS",
4009 { "spec-ctrl", "on" },
4010 { "model-id",
4011 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
4104 .alias = "Haswell-noTSX",
4109 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
4115 .alias = "Haswell-IBRS",
4117 /* Restore TSX features removed by -v2 above */
4121 * Haswell and Haswell-IBRS had stepping=4 in
4125 { "spec-ctrl", "on" },
4126 { "model-id",
4133 .alias = "Haswell-noTSX-IBRS",
4137 /* spec-ctrl was already enabled by -v3 above */
4139 { "model-id",
4235 .alias = "Broadwell-noTSX",
4239 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
4245 .alias = "Broadwell-IBRS",
4247 /* Restore TSX features removed by -v2 above */
4250 { "spec-ctrl", "on" },
4251 { "model-id",
4258 .alias = "Broadwell-noTSX-IBRS",
4262 /* spec-ctrl was already enabled by -v3 above */
4263 { "model-id",
4272 .name = "Skylake-Client",
4308 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4359 .alias = "Skylake-Client-IBRS",
4361 { "spec-ctrl", "on" },
4362 { "model-id",
4369 .alias = "Skylake-Client-noTSX-IBRS",
4373 { "model-id",
4383 { "vmx-xsaves", "on" },
4391 .name = "Skylake-Server",
4432 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4485 .alias = "Skylake-Server-IBRS",
4487 /* clflushopt was not added to Skylake-Server-IBRS */
4488 /* TODO: add -v3 including clflushopt */
4490 { "spec-ctrl", "on" },
4491 { "model-id",
4498 .alias = "Skylake-Server-noTSX-IBRS",
4502 { "model-id",
4511 { "vmx-eptp-switching", "on" },
4520 { "vmx-xsaves", "on" },
4528 .name = "Cascadelake-Server",
4572 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4626 { "arch-capabilities", "on" },
4627 { "rdctl-no", "on" },
4628 { "ibrs-all", "on" },
4629 { "skip-l1dfl-vmentry", "on" },
4630 { "mds-no", "on" },
4635 .alias = "Cascadelake-Server-noTSX",
4646 { "vmx-eptp-switching", "on" },
4654 { "vmx-xsaves", "on" },
4713 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4769 { "vmx-xsaves", "on" },
4777 .name = "Icelake-Server",
4826 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4879 .alias = "Icelake-Server-noTSX",
4889 { "arch-capabilities", "on" },
4890 { "rdctl-no", "on" },
4891 { "ibrs-all", "on" },
4892 { "skip-l1dfl-vmentry", "on" },
4893 { "mds-no", "on" },
4894 { "pschange-mc-no", "on" },
4895 { "taa-no", "on" },
4902 { "sha-ni", "on" },
4906 { "vmx-rdseed-exit", "on" },
4907 { "vmx-pml", "on" },
4908 { "vmx-eptp-switching", "on" },
4918 { "vmx-xsaves", "on" },
4924 .note = "5-level EPT",
4926 { "vmx-page-walk-5", "on" },
4932 .note = "TSX, taa-no",
4934 /* Restore TSX features removed by -v2 above */
5072 { "sbdr-ssdp-no", "on" },
5073 { "fbsdp-no", "on" },
5074 { "psdp-no", "on" },
5082 { "tsc-adjust", "on" },
5091 .note = "with spr-sp cache model and 0x1f leaf",
5094 { "x-force-cpuid-0x1f", "on" },
5238 { "tsc-adjust", "on" },
5243 { "avx10-128", "on" },
5244 { "avx10-256", "on" },
5245 { "avx10-512", "on" },
5246 { "avx10-version", "1" },
5253 .note = "with gnr-sp cache model and 0x1f leaf",
5256 { "x-force-cpuid-0x1f", "on" },
5390 { "tsc-adjust", "on" },
5394 { "gds-no", "on" },
5395 { "rfds-no", "on" },
5397 { "intel-psfd", "on"},
5398 { "ipred-ctrl", "on"},
5399 { "rrsba-ctrl", "on"},
5400 { "bhi-ctrl", "on"},
5407 .note = "with srf-sp cache model and 0x1f leaf",
5410 { "x-force-cpuid-0x1f", "on" },
5655 { "vmx-xsaves", "on" },
5778 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
5787 { "vmx-xsaves", "on" },
5793 .note = "no split lock detect, no core-capability",
5795 { "split-lock-detect", "off" },
5796 { "core-capability", "off" },
6023 .alias = "EPYC-IBPB",
6026 { "model-id",
6035 { "perfctr-core", "on" },
6039 { "model-id",
6047 { "model-id",
6048 "AMD EPYC-v4 Processor" },
6056 { "overflow-recov", "on" },
6059 { "tsc-scale", "on" },
6060 { "vmcb-clean", "on" },
6062 { "pause-filter", "on" },
6064 { "v-vmsave-vmload", "on" },
6066 { "model-id",
6067 "AMD EPYC-v5 Processor" },
6133 .name = "EPYC-Rome",
6179 .model_id = "AMD EPYC-Rome Processor",
6187 { "amd-ssbd", "on" },
6194 { "model-id",
6195 "AMD EPYC-Rome-v3 Processor" },
6204 { "model-id",
6205 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
6213 { "overflow-recov", "on" },
6216 { "tsc-scale", "on" },
6217 { "vmcb-clean", "on" },
6219 { "pause-filter", "on" },
6221 { "v-vmsave-vmload", "on" },
6223 { "model-id",
6224 "AMD EPYC-Rome-v5 Processor" },
6233 .name = "EPYC-Milan",
6284 .model_id = "AMD EPYC-Milan Processor",
6291 { "model-id",
6292 "AMD EPYC-Milan-v2 Processor" },
6295 { "stibp-always-on", "on" },
6296 { "amd-psfd", "on" },
6297 { "no-nested-data-bp", "on" },
6298 { "lfence-always-serializing", "on" },
6299 { "null-sel-clr-base", "on" },
6307 { "overflow-recov", "on" },
6310 { "tsc-scale", "on" },
6311 { "vmcb-clean", "on" },
6313 { "pause-filter", "on" },
6315 { "v-vmsave-vmload", "on" },
6317 { "model-id",
6318 "AMD EPYC-Milan-v3 Processor" },
6327 .name = "EPYC-Genoa",
6395 .model_id = "AMD EPYC-Genoa Processor",
6402 { "overflow-recov", "on" },
6405 { "tsc-scale", "on" },
6406 { "vmcb-clean", "on" },
6408 { "pause-filter", "on" },
6410 { "v-vmsave-vmload", "on" },
6412 { "fs-gs-base-ns", "on" },
6413 { "perfmon-v2", "on" },
6414 { "model-id",
6415 "AMD EPYC-Genoa-v2 Processor" },
6561 { "x-force-cpuid-0x1f", "on" },
6569 .name = "EPYC-Turin",
6648 .model_id = "AMD EPYC-Turin Processor",
6654 * We resolve CPU model aliases using -v1 when using "-machine
6673 x86_cpu_def_get_versions(model->cpudef); in x86_cpu_model_last_version()
6674 while (vdef->version) { in x86_cpu_model_last_version()
6675 v = vdef->version; in x86_cpu_model_last_version()
6684 X86CPUVersion v = model->version; in x86_cpu_model_resolve_version()
6696 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
6704 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in max_x86_cpu_realize()
6723 xcc->ordering = 9; in max_x86_cpu_class_init()
6725 xcc->max_features = true; in max_x86_cpu_class_init()
6726 xcc->model_description = in max_x86_cpu_class_init()
6730 dc->realize = max_x86_cpu_realize; in max_x86_cpu_class_init()
6736 CPUX86State *env = &cpu->env; in max_x86_cpu_initfn()
6742 if (!env->cpuid_vendor1) { in max_x86_cpu_initfn()
6746 if (!env->cpuid_model[0]) { in max_x86_cpu_initfn()
6747 object_property_set_str(OBJECT(cpu), "model-id", in max_x86_cpu_initfn()
6762 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); in feature_word_description()
6764 switch (f->type) { in feature_word_description()
6767 const char *reg = get_register_name_32(f->cpuid.reg); in feature_word_description()
6769 if (!f->cpuid.needs_ecx) { in feature_word_description()
6770 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); in feature_word_description()
6773 f->cpuid.eax, f->cpuid.ecx, reg); in feature_word_description()
6778 f->msr.index); in feature_word_description()
6789 if (cpu->filtered_features[w]) { in x86_cpu_have_filtered_features()
6800 CPUX86State *env = &cpu->env; in mark_unavailable_features()
6805 if (!cpu->force_features) { in mark_unavailable_features()
6806 env->features[w] &= ~mask; in mark_unavailable_features()
6808 cpu->filtered_features[w] |= mask; in mark_unavailable_features()
6819 f->feat_names[i] ? "." : "", in mark_unavailable_features()
6820 f->feat_names[i] ? f->feat_names[i] : "", i); in mark_unavailable_features()
6828 CPUX86State *env = &cpu->env; in mark_forced_on_features()
6832 if (!cpu->force_features) { in mark_forced_on_features()
6833 env->features[w] |= mask; in mark_forced_on_features()
6836 cpu->forced_on_features[w] |= mask; in mark_forced_on_features()
6848 f->feat_names[i] ? "." : "", in mark_forced_on_features()
6849 f->feat_names[i] ? f->feat_names[i] : "", i); in mark_forced_on_features()
6859 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_family()
6862 value = x86_cpu_family(env->cpuid_version); in x86_cpuid_version_get_family()
6871 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_family()
6884 env->cpuid_version &= ~0xff00f00; in x86_cpuid_version_set_family()
6886 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); in x86_cpuid_version_set_family()
6888 env->cpuid_version |= value << 8; in x86_cpuid_version_set_family()
6897 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_model()
6900 value = x86_cpu_model(env->cpuid_version); in x86_cpuid_version_get_model()
6909 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_model()
6922 env->cpuid_version &= ~0xf00f0; in x86_cpuid_version_set_model()
6923 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); in x86_cpuid_version_set_model()
6931 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_stepping()
6934 value = x86_cpu_stepping(env->cpuid_version); in x86_cpuid_version_get_stepping()
6943 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_stepping()
6956 env->cpuid_version &= ~0xf; in x86_cpuid_version_set_stepping()
6957 env->cpuid_version |= value & 0xf; in x86_cpuid_version_set_stepping()
6963 CPUX86State *env = &cpu->env; in x86_cpuid_get_vendor()
6967 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, in x86_cpuid_get_vendor()
6968 env->cpuid_vendor3); in x86_cpuid_get_vendor()
6976 CPUX86State *env = &cpu->env; in x86_cpuid_set_vendor()
6985 env->cpuid_vendor1 = 0; in x86_cpuid_set_vendor()
6986 env->cpuid_vendor2 = 0; in x86_cpuid_set_vendor()
6987 env->cpuid_vendor3 = 0; in x86_cpuid_set_vendor()
6989 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); in x86_cpuid_set_vendor()
6990 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); in x86_cpuid_set_vendor()
6991 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); in x86_cpuid_set_vendor()
6998 CPUX86State *env = &cpu->env; in x86_cpuid_get_model_id()
7004 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); in x86_cpuid_get_model_id()
7014 CPUX86State *env = &cpu->env; in x86_cpuid_set_model_id()
7021 memset(env->cpuid_model, 0, CPUID_MODEL_ID_SZ); in x86_cpuid_set_model_id()
7028 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); in x86_cpuid_set_model_id()
7038 value = cpu->env.tsc_khz * 1000; in x86_cpuid_get_tsc_freq()
7058 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; in x86_cpuid_set_tsc_freq()
7061 /* Generic getter for "feature-words" and "filtered-features" properties */
7075 * We didn't have MSR features when "feature-words" was in x86_cpu_get_feature_words()
7078 if (wi->type != CPUID_FEATURE_WORD) { in x86_cpu_get_feature_words()
7082 qwi->cpuid_input_eax = wi->cpuid.eax; in x86_cpu_get_feature_words()
7083 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; in x86_cpu_get_feature_words()
7084 qwi->cpuid_input_ecx = wi->cpuid.ecx; in x86_cpu_get_feature_words()
7085 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; in x86_cpu_get_feature_words()
7086 qwi->features = array[w]; in x86_cpu_get_feature_words()
7094 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); in x86_cpu_get_feature_words()
7097 /* Convert all '_' in a feature string option name to '-', to make feature
7098 * name conform to QOM property naming rule, which uses '-' instead of '_'.
7103 *s = '-'; in feat2prop()
7131 /* Compatibility hack to maintain legacy +-feat semantic,
7132 * where +-feat overwrites any feature set by
7133 * feat=on|feat even if the later is parsed after +-feat
7134 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
7143 /* Parse "+feature,-feature,feature=foo" CPU feature string
7175 } else if (featurestr[0] == '-') { in x86_cpu_parse_featurestr()
7200 "Don't mix both \"-%s\" and \"%s=%s\"", in x86_cpu_parse_featurestr()
7206 if (!strcmp(name, "tsc-freq")) { in x86_cpu_parse_featurestr()
7217 name = "tsc-frequency"; in x86_cpu_parse_featurestr()
7221 prop->driver = typename; in x86_cpu_parse_featurestr()
7222 prop->property = g_strdup(name); in x86_cpu_parse_featurestr()
7223 prop->value = g_strdup(val); in x86_cpu_parse_featurestr()
7260 x86_cpu_list_feature_names(xc->filtered_features, &result); in x86_cpu_get_unavailable_features()
7261 visit_type_strList(v, "unavailable-features", &result, errp); in x86_cpu_get_unavailable_features()
7271 for (tmp = features; tmp; tmp = tmp->next) { in listflags()
7272 const char *name = tmp->data; in listflags()
7292 if (cc_a->ordering != cc_b->ordering) { in x86_cpu_list_compare()
7293 ret = cc_a->ordering - cc_b->ordering; in x86_cpu_list_compare()
7312 char *r = object_property_get_str(obj, "model-id", &error_abort); in x86_cpu_class_get_model_id()
7321 if (!cc->model || !cc->model->is_alias) { in x86_cpu_class_get_alias_of()
7324 version = x86_cpu_model_resolve_version(cc->model); in x86_cpu_class_get_alias_of()
7328 return x86_cpu_versioned_model_name(cc->model->cpudef, version); in x86_cpu_class_get_alias_of()
7336 g_autofree char *desc = g_strdup(cc->model_description); in x86_cpu_list_entry()
7341 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { in x86_cpu_list_entry()
7347 if (!desc && cc->model && cc->model->note) { in x86_cpu_list_entry()
7348 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); in x86_cpu_list_entry()
7354 if (cc->model && cc->model->cpudef->deprecation_note) { in x86_cpu_list_entry()
7359 qemu_printf(" %-20s %s\n", name, desc); in x86_cpu_list_entry()
7383 if (fw->feat_names[j]) { in x86_cpu_list()
7384 names = g_list_append(names, (gpointer)fw->feat_names[j]); in x86_cpu_list()
7409 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { in x86_cpu_class_check_missing_features()
7428 x86_cpu_list_feature_names(xc->filtered_features, tail); in x86_cpu_class_check_missing_features()
7441 info->name = x86_cpu_class_get_model_name(cc); in x86_cpu_definition_entry()
7442 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); in x86_cpu_definition_entry()
7443 info->has_unavailable_features = true; in x86_cpu_definition_entry()
7444 info->q_typename = g_strdup(object_class_get_name(oc)); in x86_cpu_definition_entry()
7445 info->migration_safe = cc->migration_safe; in x86_cpu_definition_entry()
7446 info->has_migration_safe = true; in x86_cpu_definition_entry()
7447 info->q_static = cc->static_model; in x86_cpu_definition_entry()
7448 if (cc->model && cc->model->cpudef->deprecation_note) { in x86_cpu_definition_entry()
7449 info->deprecated = true; in x86_cpu_definition_entry()
7451 info->deprecated = false; in x86_cpu_definition_entry()
7458 info->alias_of = x86_cpu_class_get_alias_of(cc); in x86_cpu_definition_entry()
7482 switch (wi->type) { in x86_cpu_get_supported_feature_word()
7484 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, in x86_cpu_get_supported_feature_word()
7485 wi->cpuid.ecx, in x86_cpu_get_supported_feature_word()
7486 wi->cpuid.reg); in x86_cpu_get_supported_feature_word()
7490 wi->msr.index); in x86_cpu_get_supported_feature_word()
7494 if (wi->type != CPUID_FEATURE_WORD) { in x86_cpu_get_supported_feature_word()
7497 r = hvf_get_supported_cpuid(wi->cpuid.eax, in x86_cpu_get_supported_feature_word()
7498 wi->cpuid.ecx, in x86_cpu_get_supported_feature_word()
7499 wi->cpuid.reg); in x86_cpu_get_supported_feature_word()
7501 r = wi->tcg_features; in x86_cpu_get_supported_feature_word()
7510 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no in x86_cpu_get_supported_feature_word()
7511 * way for userspace to get out of its 32-bit jail, we can leave in x86_cpu_get_supported_feature_word()
7521 if (cpu && !IS_AMD_CPU(&cpu->env)) { in x86_cpu_get_supported_feature_word()
7551 if (cpu && IS_AMD_CPU(&cpu->env) && !cpu->arch_cap_always_on) { in x86_cpu_get_supported_feature_word()
7561 if (cpu && cpu->migratable) { in x86_cpu_get_supported_feature_word()
7626 for (pv = props; pv->prop; pv++) { in x86_cpu_apply_props()
7627 if (!pv->value) { in x86_cpu_apply_props()
7630 object_property_parse(OBJECT(cpu), pv->prop, pv->value, in x86_cpu_apply_props()
7649 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { in x86_cpu_apply_version_props()
7652 for (p = vdef->props; p && p->prop; p++) { in x86_cpu_apply_version_props()
7653 object_property_parse(OBJECT(cpu), p->prop, p->value, in x86_cpu_apply_version_props()
7657 if (vdef->version == version) { in x86_cpu_apply_version_props()
7665 assert(vdef->version == version); in x86_cpu_apply_version_props()
7673 const CPUCaches *cache_info = model->cpudef->cache_info; in x86_cpu_get_versioned_cache_info()
7679 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { in x86_cpu_get_versioned_cache_info()
7680 if (vdef->cache_info) { in x86_cpu_get_versioned_cache_info()
7681 cache_info = vdef->cache_info; in x86_cpu_get_versioned_cache_info()
7684 if (vdef->version == version) { in x86_cpu_get_versioned_cache_info()
7689 assert(vdef->version == version); in x86_cpu_get_versioned_cache_info()
7699 const X86CPUDefinition *def = model->cpudef; in x86_cpu_load_model()
7700 CPUX86State *env = &cpu->env; in x86_cpu_load_model()
7705 * query-cpu-model-expansion is always complete. in x86_cpu_load_model()
7709 object_property_set_uint(OBJECT(cpu), "min-level", def->level, in x86_cpu_load_model()
7711 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, in x86_cpu_load_model()
7714 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); in x86_cpu_load_model()
7715 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); in x86_cpu_load_model()
7716 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, in x86_cpu_load_model()
7718 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, in x86_cpu_load_model()
7721 env->features[w] = def->features[w]; in x86_cpu_load_model()
7724 /* legacy-cache defaults to 'off' if CPU model provides cache info */ in x86_cpu_load_model()
7725 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); in x86_cpu_load_model()
7727 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; in x86_cpu_load_model()
7734 * when doing cross vendor migration in x86_cpu_load_model()
7741 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); in x86_cpu_load_model()
7743 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, in x86_cpu_load_model()
7750 * We can simply clear env->user_features here since it will be filled later in x86_cpu_load_model()
7753 memset(&env->user_features, 0, sizeof(env->user_features)); in x86_cpu_load_model()
7759 return "i386:x86-64"; in x86_gdb_arch_name()
7771 xcc->model = model; in x86_cpu_cpudef_class_init()
7772 xcc->migration_safe = true; in x86_cpu_cpudef_class_init()
7773 cc->deprecation_note = model->cpudef->deprecation_note; in x86_cpu_cpudef_class_init()
7803 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); in x86_register_cpudef_types()
7805 assert(def->model_id && strlen(def->model_id) <= 48); in x86_register_cpudef_types()
7809 m->cpudef = def; in x86_register_cpudef_types()
7810 m->version = CPU_VERSION_AUTO; in x86_register_cpudef_types()
7811 m->is_alias = true; in x86_register_cpudef_types()
7812 x86_register_cpu_model_type(def->name, m); in x86_register_cpudef_types()
7816 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { in x86_register_cpudef_types()
7818 x86_cpu_versioned_model_name(def, vdef->version); in x86_register_cpudef_types()
7821 m->cpudef = def; in x86_register_cpudef_types()
7822 m->version = vdef->version; in x86_register_cpudef_types()
7823 m->note = vdef->note; in x86_register_cpudef_types()
7826 if (vdef->alias) { in x86_register_cpudef_types()
7828 am->cpudef = def; in x86_register_cpudef_types()
7829 am->version = vdef->version; in x86_register_cpudef_types()
7830 am->is_alias = true; in x86_register_cpudef_types()
7831 x86_register_cpu_model_type(vdef->alias, am); in x86_register_cpudef_types()
7839 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { in cpu_x86_virtual_addr_width()
7854 X86CPUTopoInfo *topo_info = &env->topo_info; in cpu_x86_cpuid()
7861 limit = env->cpuid_xlevel2; in cpu_x86_cpuid()
7863 limit = env->cpuid_xlevel; in cpu_x86_cpuid()
7867 limit = env->cpuid_level; in cpu_x86_cpuid()
7873 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) in cpu_x86_cpuid()
7875 index = env->cpuid_level; in cpu_x86_cpuid()
7880 *eax = env->cpuid_level; in cpu_x86_cpuid()
7881 *ebx = env->cpuid_vendor1; in cpu_x86_cpuid()
7882 *edx = env->cpuid_vendor2; in cpu_x86_cpuid()
7883 *ecx = env->cpuid_vendor3; in cpu_x86_cpuid()
7886 *eax = env->cpuid_version; in cpu_x86_cpuid()
7887 *ebx = (cpu->apic_id << 24) | in cpu_x86_cpuid()
7889 *ecx = env->features[FEAT_1_ECX]; in cpu_x86_cpuid()
7890 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { in cpu_x86_cpuid()
7893 *edx = env->features[FEAT_1_EDX]; in cpu_x86_cpuid()
7898 * For CPUID.01H.EBX[Bits 23-16], AMD requires logical processor in cpu_x86_cpuid()
7908 /* Fixup overflow: max value for bits 23-16 is 255. */ in cpu_x86_cpuid()
7911 if (cpu->pdcm_on_even_without_pmu) { in cpu_x86_cpuid()
7912 if (!cpu->enable_pmu) { in cpu_x86_cpuid()
7920 if (env->enable_legacy_cpuid2_cache) { in cpu_x86_cpuid()
7922 } else if (env->enable_legacy_vendor_cache) { in cpu_x86_cpuid()
7925 caches = &env->cache_info; in cpu_x86_cpuid()
7928 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7931 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { in cpu_x86_cpuid()
7941 if (env->enable_legacy_vendor_cache) { in cpu_x86_cpuid()
7944 caches = &env->cache_info; in cpu_x86_cpuid()
7948 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7967 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { in cpu_x86_cpuid()
7974 encode_cache_cpuid4(caches->l1d_cache, topo_info, in cpu_x86_cpuid()
7976 if (!cpu->l1_cache_per_core) { in cpu_x86_cpuid()
7981 encode_cache_cpuid4(caches->l1i_cache, topo_info, in cpu_x86_cpuid()
7983 if (!cpu->l1_cache_per_core) { in cpu_x86_cpuid()
7988 encode_cache_cpuid4(caches->l2_cache, topo_info, in cpu_x86_cpuid()
7992 if (cpu->enable_l3_cache) { in cpu_x86_cpuid()
7993 encode_cache_cpuid4(caches->l3_cache, topo_info, in cpu_x86_cpuid()
8007 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ in cpu_x86_cpuid()
8008 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ in cpu_x86_cpuid()
8009 *ecx = cpu->mwait.ecx; /* flags */ in cpu_x86_cpuid()
8010 *edx = cpu->mwait.edx; /* mwait substates */ in cpu_x86_cpuid()
8014 *eax = env->features[FEAT_6_EAX]; in cpu_x86_cpuid()
8022 /* Maximum ECX value for sub-leaves */ in cpu_x86_cpuid()
8023 *eax = env->cpuid_level_func7; in cpu_x86_cpuid()
8024 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ in cpu_x86_cpuid()
8025 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ in cpu_x86_cpuid()
8026 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { in cpu_x86_cpuid()
8029 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ in cpu_x86_cpuid()
8031 *eax = env->features[FEAT_7_1_EAX]; in cpu_x86_cpuid()
8032 *ecx = env->features[FEAT_7_1_ECX]; in cpu_x86_cpuid()
8033 *edx = env->features[FEAT_7_1_EDX]; in cpu_x86_cpuid()
8036 *edx = env->features[FEAT_7_2_EDX]; in cpu_x86_cpuid()
8049 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ in cpu_x86_cpuid()
8056 if (cpu->enable_pmu) { in cpu_x86_cpuid()
8067 if (!cpu->enable_cpuid_0xb) { in cpu_x86_cpuid()
8073 *edx = cpu->apic_id; in cpu_x86_cpuid()
8078 *ebx = topo_info->threads_per_core; in cpu_x86_cpuid()
8101 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { in cpu_x86_cpuid()
8107 *eax = env->features[FEAT_XSAVE_XCR0_LO]; in cpu_x86_cpuid()
8108 *edx = env->features[FEAT_XSAVE_XCR0_HI]; in cpu_x86_cpuid()
8115 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); in cpu_x86_cpuid()
8120 *eax = env->features[FEAT_XSAVE]; in cpu_x86_cpuid()
8122 *ecx = env->features[FEAT_XSAVE_XSS_LO]; in cpu_x86_cpuid()
8123 *edx = env->features[FEAT_XSAVE_XSS_HI]; in cpu_x86_cpuid()
8124 if (kvm_enabled() && cpu->enable_pmu && in cpu_x86_cpuid()
8125 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && in cpu_x86_cpuid()
8131 } else if (count == 0xf && cpu->enable_pmu in cpu_x86_cpuid()
8132 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { in cpu_x86_cpuid()
8138 *eax = esa->size; in cpu_x86_cpuid()
8139 *ebx = esa->offset; in cpu_x86_cpuid()
8140 *ecx = esa->ecx & in cpu_x86_cpuid()
8143 *eax = esa->size; in cpu_x86_cpuid()
8153 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { in cpu_x86_cpuid()
8159 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve in cpu_x86_cpuid()
8167 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { in cpu_x86_cpuid()
8180 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware in cpu_x86_cpuid()
8188 *eax &= env->features[FEAT_SGX_12_0_EAX]; in cpu_x86_cpuid()
8189 *ebx &= env->features[FEAT_SGX_12_0_EBX]; in cpu_x86_cpuid()
8191 *eax &= env->features[FEAT_SGX_12_1_EAX]; in cpu_x86_cpuid()
8193 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; in cpu_x86_cpuid()
8194 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; in cpu_x86_cpuid()
8201 !kvm_enable_sgx_provisioning(cs->kvm_state)) { in cpu_x86_cpuid()
8213 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || in cpu_x86_cpuid()
8226 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { in cpu_x86_cpuid()
8236 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { in cpu_x86_cpuid()
8247 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { in cpu_x86_cpuid()
8268 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { in cpu_x86_cpuid()
8292 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { in cpu_x86_cpuid()
8293 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; in cpu_x86_cpuid()
8302 if (tcg_enabled() && cpu->expose_tcg) { in cpu_x86_cpuid()
8322 *eax = env->cpuid_xlevel; in cpu_x86_cpuid()
8324 if (cpu->vendor_cpuid_only_v2 && in cpu_x86_cpuid()
8328 *ebx = env->cpuid_vendor1; in cpu_x86_cpuid()
8329 *edx = env->cpuid_vendor2; in cpu_x86_cpuid()
8330 *ecx = env->cpuid_vendor3; in cpu_x86_cpuid()
8334 *eax = env->cpuid_version; in cpu_x86_cpuid()
8336 *ecx = env->features[FEAT_8000_0001_ECX]; in cpu_x86_cpuid()
8337 *edx = env->features[FEAT_8000_0001_EDX]; in cpu_x86_cpuid()
8340 !(env->hflags & HF_LMA_MASK)) { in cpu_x86_cpuid()
8347 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; in cpu_x86_cpuid()
8348 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; in cpu_x86_cpuid()
8349 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; in cpu_x86_cpuid()
8350 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; in cpu_x86_cpuid()
8356 if (env->enable_legacy_vendor_cache) { in cpu_x86_cpuid()
8359 caches = &env->cache_info; in cpu_x86_cpuid()
8362 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
8367 if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { in cpu_x86_cpuid()
8376 *ecx = encode_cache_cpuid80000005(caches->l1d_cache); in cpu_x86_cpuid()
8377 *edx = encode_cache_cpuid80000005(caches->l1i_cache); in cpu_x86_cpuid()
8383 if (env->enable_legacy_vendor_cache) { in cpu_x86_cpuid()
8386 caches = &env->cache_info; in cpu_x86_cpuid()
8389 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
8394 if (cpu->vendor_cpuid_only_v2 && in cpu_x86_cpuid()
8397 encode_cache_cpuid80000006(caches->l2_cache, in cpu_x86_cpuid()
8411 encode_cache_cpuid80000006(caches->l2_cache, in cpu_x86_cpuid()
8412 cpu->enable_l3_cache ? in cpu_x86_cpuid()
8413 caches->l3_cache : NULL, in cpu_x86_cpuid()
8419 if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { in cpu_x86_cpuid()
8422 *ebx = env->features[FEAT_8000_0007_EBX]; in cpu_x86_cpuid()
8425 *edx = env->features[FEAT_8000_0007_EDX]; in cpu_x86_cpuid()
8429 *eax = cpu->phys_bits; in cpu_x86_cpuid()
8430 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in cpu_x86_cpuid()
8433 *eax |= (cpu->guest_phys_bits << 16); in cpu_x86_cpuid()
8435 *ebx = env->features[FEAT_8000_0008_EBX]; in cpu_x86_cpuid()
8441 if (cpu->vendor_cpuid_only_v2 && in cpu_x86_cpuid()
8455 (threads_per_pkg - 1); in cpu_x86_cpuid()
8462 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { in cpu_x86_cpuid()
8466 *edx = env->features[FEAT_SVM]; /* optional features */ in cpu_x86_cpuid()
8476 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
8482 encode_cache_cpuid8000001d(env->cache_info.l1d_cache, in cpu_x86_cpuid()
8486 encode_cache_cpuid8000001d(env->cache_info.l1i_cache, in cpu_x86_cpuid()
8490 encode_cache_cpuid8000001d(env->cache_info.l2_cache, in cpu_x86_cpuid()
8494 encode_cache_cpuid8000001d(env->cache_info.l3_cache, in cpu_x86_cpuid()
8501 if (cpu->amd_topoext_features_only) { in cpu_x86_cpuid()
8506 if (cpu->core_id <= 255) { in cpu_x86_cpuid()
8527 *eax = env->features[FEAT_8000_0021_EAX]; in cpu_x86_cpuid()
8528 *ebx = env->features[FEAT_8000_0021_EBX]; in cpu_x86_cpuid()
8533 if (kvm_enabled() && cpu->enable_pmu && in cpu_x86_cpuid()
8534 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { in cpu_x86_cpuid()
8536 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, in cpu_x86_cpuid()
8541 *eax = env->cpuid_xlevel2; in cpu_x86_cpuid()
8548 *eax = env->cpuid_version; in cpu_x86_cpuid()
8551 *edx = env->features[FEAT_C000_0001_EDX]; in cpu_x86_cpuid()
8576 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; in x86_cpu_set_sgxlepubkeyhash()
8577 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; in x86_cpu_set_sgxlepubkeyhash()
8578 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; in x86_cpu_set_sgxlepubkeyhash()
8579 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; in x86_cpu_set_sgxlepubkeyhash()
8585 if (!esa->size) { in cpuid_has_xsave_feature()
8589 if (env->features[esa->feature] & esa->bits) { in cpuid_has_xsave_feature()
8592 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F in cpuid_has_xsave_feature()
8593 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { in cpuid_has_xsave_feature()
8605 CPUX86State *env = &cpu->env; in x86_cpu_reset_hold()
8610 if (xcc->parent_phases.hold) { in x86_cpu_reset_hold()
8611 xcc->parent_phases.hold(obj, type); in x86_cpu_reset_hold()
8620 env->old_exception = -1; in x86_cpu_reset_hold()
8623 env->int_ctl = 0; in x86_cpu_reset_hold()
8624 env->hflags2 |= HF2_GIF_MASK; in x86_cpu_reset_hold()
8625 env->hflags2 |= HF2_VGIF_MASK; in x86_cpu_reset_hold()
8626 env->hflags &= ~HF_GUEST_MASK; in x86_cpu_reset_hold()
8629 env->a20_mask = ~0x0; in x86_cpu_reset_hold()
8630 env->smbase = 0x30000; in x86_cpu_reset_hold()
8631 env->msr_smi_count = 0; in x86_cpu_reset_hold()
8633 env->idt.limit = 0xffff; in x86_cpu_reset_hold()
8634 env->gdt.limit = 0xffff; in x86_cpu_reset_hold()
8636 env->ldt.limit = 0; in x86_cpu_reset_hold()
8638 env->ldt.limit = 0xffff; in x86_cpu_reset_hold()
8640 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); in x86_cpu_reset_hold()
8641 env->tr.limit = 0xffff; in x86_cpu_reset_hold()
8642 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); in x86_cpu_reset_hold()
8663 env->eip = 0xfff0; in x86_cpu_reset_hold()
8664 env->regs[R_EDX] = env->cpuid_version; in x86_cpu_reset_hold()
8666 env->eflags = 0x2; in x86_cpu_reset_hold()
8670 env->fptags[i] = 1; in x86_cpu_reset_hold()
8674 env->mxcsr = 0x1f80; in x86_cpu_reset_hold()
8676 env->xstate_bv = 0; in x86_cpu_reset_hold()
8678 env->pat = 0x0007040600070406ULL; in x86_cpu_reset_hold()
8682 * KVM handles TSC = 0 specially and thinks we are hot-plugging in x86_cpu_reset_hold()
8685 if (env->tsc != 0) { in x86_cpu_reset_hold()
8686 env->tsc = 1; in x86_cpu_reset_hold()
8689 env->tsc = 0; in x86_cpu_reset_hold()
8692 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; in x86_cpu_reset_hold()
8693 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { in x86_cpu_reset_hold()
8694 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; in x86_cpu_reset_hold()
8697 memset(env->dr, 0, sizeof(env->dr)); in x86_cpu_reset_hold()
8698 env->dr[6] = DR6_FIXED_1; in x86_cpu_reset_hold()
8699 env->dr[7] = DR7_FIXED_1; in x86_cpu_reset_hold()
8707 /* Enable all the features for user-mode. */ in x86_cpu_reset_hold()
8708 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in x86_cpu_reset_hold()
8721 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { in x86_cpu_reset_hold()
8724 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { in x86_cpu_reset_hold()
8729 env->xcr0 = xcr0; in x86_cpu_reset_hold()
8734 * - IA32_MTRR_DEF_TYPE MSR.E = 0 in x86_cpu_reset_hold()
8735 * - IA32_MTRR_PHYSMASKn.V = 0 in x86_cpu_reset_hold()
8738 env->mtrr_deftype = 0; in x86_cpu_reset_hold()
8739 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); in x86_cpu_reset_hold()
8740 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); in x86_cpu_reset_hold()
8742 env->interrupt_injected = -1; in x86_cpu_reset_hold()
8743 env->exception_nr = -1; in x86_cpu_reset_hold()
8744 env->exception_pending = 0; in x86_cpu_reset_hold()
8745 env->exception_injected = 0; in x86_cpu_reset_hold()
8746 env->exception_has_payload = false; in x86_cpu_reset_hold()
8747 env->exception_payload = 0; in x86_cpu_reset_hold()
8748 env->nmi_injected = false; in x86_cpu_reset_hold()
8749 env->triple_fault_pending = false; in x86_cpu_reset_hold()
8751 /* We hard-wire the BSP to the first CPU. */ in x86_cpu_reset_hold()
8752 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); in x86_cpu_reset_hold()
8754 cs->halted = !cpu_is_bsp(cpu); in x86_cpu_reset_hold()
8762 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; in x86_cpu_reset_hold()
8774 if (cpu->apic_state) { in x86_cpu_after_reset()
8775 device_cold_reset(cpu->apic_state); in x86_cpu_after_reset()
8782 CPUX86State *cenv = &cpu->env; in mce_init()
8785 if (x86_cpu_family(cenv->cpuid_version) >= 6 in mce_init()
8786 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == in mce_init()
8788 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | in mce_init()
8789 (cpu->enable_lmce ? MCG_LMCE_P : 0); in mce_init()
8790 cenv->mcg_ctl = ~(uint64_t)0; in mce_init()
8792 cenv->mce_banks[bank * 4] = ~(uint64_t)0; in mce_init()
8807 CPUX86State *env = &cpu->env; in x86_cpu_adjust_feat_level()
8809 uint32_t eax = fi->cpuid.eax; in x86_cpu_adjust_feat_level()
8813 if (!env->features[w]) { in x86_cpu_adjust_feat_level()
8819 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); in x86_cpu_adjust_feat_level()
8822 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); in x86_cpu_adjust_feat_level()
8825 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); in x86_cpu_adjust_feat_level()
8830 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, in x86_cpu_adjust_feat_level()
8831 fi->cpuid.ecx); in x86_cpu_adjust_feat_level()
8838 CPUX86State *env = &cpu->env; in x86_cpu_enable_xsave_components()
8843 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { in x86_cpu_enable_xsave_components()
8844 env->features[FEAT_XSAVE_XCR0_LO] = 0; in x86_cpu_enable_xsave_components()
8845 env->features[FEAT_XSAVE_XCR0_HI] = 0; in x86_cpu_enable_xsave_components()
8846 env->features[FEAT_XSAVE_XSS_LO] = 0; in x86_cpu_enable_xsave_components()
8847 env->features[FEAT_XSAVE_XSS_HI] = 0; in x86_cpu_enable_xsave_components()
8865 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; in x86_cpu_enable_xsave_components()
8866 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; in x86_cpu_enable_xsave_components()
8867 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; in x86_cpu_enable_xsave_components()
8868 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; in x86_cpu_enable_xsave_components()
8895 * - CPU instance creation (instance_init) will run only CPU
8896 * model loading. CPU expansion can't run at instance_init-time
8898 * - CPU realization will perform both CPU model expansion and CPUID
8900 * - query-cpu-definitions needs to run all 3 steps. It needs
8901 * to run CPUID filtering, as the 'unavailable-features'
8903 * - The query-cpu-model-expansion QMP command only needs to run
8914 CPUX86State *env = &cpu->env; in x86_cpu_expand_features()
8919 for (l = plus_features; l; l = l->next) { in x86_cpu_expand_features()
8920 const char *prop = l->data; in x86_cpu_expand_features()
8926 for (l = minus_features; l; l = l->next) { in x86_cpu_expand_features()
8927 const char *prop = l->data; in x86_cpu_expand_features()
8933 /* TODO: Now xcc->max_features doesn't overwrite features in x86_cpu_expand_features()
8938 if (xcc->max_features) { in x86_cpu_expand_features()
8943 env->features[w] |= in x86_cpu_expand_features()
8945 ~env->user_features[w] & in x86_cpu_expand_features()
8949 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { in x86_cpu_expand_features()
8952 env->avx10_version = ebx & 0xff; in x86_cpu_expand_features()
8956 if (x86_threads_per_pkg(&env->topo_info) > 1) { in x86_cpu_expand_features()
8957 env->features[FEAT_1_EDX] |= CPUID_HT; in x86_cpu_expand_features()
8966 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; in x86_cpu_expand_features()
8970 if (!cpu->pdcm_on_even_without_pmu) { in x86_cpu_expand_features()
8972 if (!cpu->enable_pmu && !is_tdx_vm()) { in x86_cpu_expand_features()
8973 env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; in x86_cpu_expand_features()
8979 if (!(env->features[d->from.index] & d->from.mask)) { in x86_cpu_expand_features()
8980 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; in x86_cpu_expand_features()
8983 mark_unavailable_features(cpu, d->to.index, in x86_cpu_expand_features()
8984 unavailable_features & env->user_features[d->to.index], in x86_cpu_expand_features()
8987 env->features[d->to.index] &= ~unavailable_features; in x86_cpu_expand_features()
8991 if (!kvm_enabled() || !cpu->expose_kvm) { in x86_cpu_expand_features()
8992 env->features[FEAT_KVM] = 0; in x86_cpu_expand_features()
8999 if (cpu->full_cpuid_auto_level) { in x86_cpu_expand_features()
9017 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { in x86_cpu_expand_features()
9018 if (cpu->intel_pt_auto_level) { in x86_cpu_expand_features()
9019 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); in x86_cpu_expand_features()
9020 } else if (cpu->env.cpuid_min_level < 0x14) { in x86_cpu_expand_features()
9023 … "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); in x86_cpu_expand_features()
9028 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. in x86_cpu_expand_features()
9031 * cpu->vendor_cpuid_only has been unset for compatibility with older in x86_cpu_expand_features()
9035 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { in x86_cpu_expand_features()
9036 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); in x86_cpu_expand_features()
9040 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { in x86_cpu_expand_features()
9041 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); in x86_cpu_expand_features()
9045 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { in x86_cpu_expand_features()
9046 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); in x86_cpu_expand_features()
9051 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); in x86_cpu_expand_features()
9054 if (env->features[FEAT_8000_0021_EAX]) { in x86_cpu_expand_features()
9055 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); in x86_cpu_expand_features()
9059 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { in x86_cpu_expand_features()
9060 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); in x86_cpu_expand_features()
9065 if (env->cpuid_level_func7 == UINT32_MAX) { in x86_cpu_expand_features()
9066 env->cpuid_level_func7 = env->cpuid_min_level_func7; in x86_cpu_expand_features()
9068 if (env->cpuid_level == UINT32_MAX) { in x86_cpu_expand_features()
9069 env->cpuid_level = env->cpuid_min_level; in x86_cpu_expand_features()
9071 if (env->cpuid_xlevel == UINT32_MAX) { in x86_cpu_expand_features()
9072 env->cpuid_xlevel = env->cpuid_min_xlevel; in x86_cpu_expand_features()
9074 if (env->cpuid_xlevel2 == UINT32_MAX) { in x86_cpu_expand_features()
9075 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; in x86_cpu_expand_features()
9091 CPUX86State *env = &cpu->env; in x86_cpu_filter_features()
9108 uint64_t requested_features = env->features[w]; in x86_cpu_filter_features()
9117 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && in x86_cpu_filter_features()
9133 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { in x86_cpu_filter_features()
9137 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. in x86_cpu_filter_features()
9145 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { in x86_cpu_filter_features()
9150 if (version < env->avx10_version) { in x86_cpu_filter_features()
9153 prefix, env->avx10_version, version); in x86_cpu_filter_features()
9155 env->avx10_version = version; in x86_cpu_filter_features()
9158 } else if (env->avx10_version) { in x86_cpu_filter_features()
9160 warn_report("%s: avx10.%d.", prefix, env->avx10_version); in x86_cpu_filter_features()
9172 /* Hyper-V vendor id */ in x86_cpu_hyperv_realize()
9173 if (!cpu->hyperv_vendor) { in x86_cpu_hyperv_realize()
9174 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", in x86_cpu_hyperv_realize()
9177 len = strlen(cpu->hyperv_vendor); in x86_cpu_hyperv_realize()
9179 warn_report("hv-vendor-id truncated to 12 characters"); in x86_cpu_hyperv_realize()
9182 memset(cpu->hyperv_vendor_id, 0, 12); in x86_cpu_hyperv_realize()
9183 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); in x86_cpu_hyperv_realize()
9186 cpu->hyperv_interface_id[0] = 0x31237648; in x86_cpu_hyperv_realize()
9187 cpu->hyperv_interface_id[1] = 0; in x86_cpu_hyperv_realize()
9188 cpu->hyperv_interface_id[2] = 0; in x86_cpu_hyperv_realize()
9189 cpu->hyperv_interface_id[3] = 0; in x86_cpu_hyperv_realize()
9192 cpu->hyperv_limits[0] = 64; in x86_cpu_hyperv_realize()
9193 cpu->hyperv_limits[1] = 0; in x86_cpu_hyperv_realize()
9194 cpu->hyperv_limits[2] = 0; in x86_cpu_hyperv_realize()
9201 CPUX86State *env = &cpu->env; in x86_cpu_update_smp_cache_topo()
9206 env->cache_info.l1d_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
9209 env->cache_info.l1d_cache->share_level); in x86_cpu_update_smp_cache_topo()
9214 env->cache_info.l1i_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
9217 env->cache_info.l1i_cache->share_level); in x86_cpu_update_smp_cache_topo()
9222 env->cache_info.l2_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
9225 env->cache_info.l2_cache->share_level); in x86_cpu_update_smp_cache_topo()
9230 env->cache_info.l3_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
9233 env->cache_info.l3_cache->share_level); in x86_cpu_update_smp_cache_topo()
9248 CPUX86State *env = &cpu->env; in x86_cpu_realizefn()
9253 /* Use pc-relative instructions in system-mode */ in x86_cpu_realizefn()
9258 * x-vendor-cpuid-only and v2 should be initernal only. But in x86_cpu_realizefn()
9261 if (!cpu->vendor_cpuid_only && cpu->vendor_cpuid_only_v2) { in x86_cpu_realizefn()
9262 error_setg(errp, "x-vendor-cpuid-only-v2 property " in x86_cpu_realizefn()
9263 "depends on x-vendor-cpuid-only"); in x86_cpu_realizefn()
9267 if (cpu->apic_id == UNASSIGNED_APIC_ID) { in x86_cpu_realizefn()
9268 error_setg(errp, "apic-id property was not initialized properly"); in x86_cpu_realizefn()
9273 * Process Hyper-V enlightenments. in x86_cpu_realizefn()
9284 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT in x86_cpu_realizefn()
9285 * with user-provided setting. in x86_cpu_realizefn()
9287 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { in x86_cpu_realizefn()
9288 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { in x86_cpu_realizefn()
9289 error_setg(errp, "invalid lbr-fmt"); in x86_cpu_realizefn()
9292 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; in x86_cpu_realizefn()
9293 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; in x86_cpu_realizefn()
9301 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; in x86_cpu_realizefn()
9307 if (!cpu->enable_pmu) { in x86_cpu_realizefn()
9312 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " in x86_cpu_realizefn()
9319 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { in x86_cpu_realizefn()
9320 if (cpu->enforce_cpuid) { in x86_cpu_realizefn()
9333 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; in x86_cpu_realizefn()
9334 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] in x86_cpu_realizefn()
9343 * These may be set by the accel-specific code, in x86_cpu_realizefn()
9352 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { in x86_cpu_realizefn()
9358 if (cpu->guest_phys_bits == -1) { in x86_cpu_realizefn()
9363 cpu->guest_phys_bits = 0; in x86_cpu_realizefn()
9366 if (cpu->ucode_rev == 0) { in x86_cpu_realizefn()
9370 * accel-specific code in cpu_exec_realizefn. in x86_cpu_realizefn()
9373 cpu->ucode_rev = 0x01000065; in x86_cpu_realizefn()
9375 cpu->ucode_rev = 0x100000000ULL; in x86_cpu_realizefn()
9383 * requires the accel-specific code in cpu_exec_realizefn to in x86_cpu_realizefn()
9384 * have already acquired the CPUID data into cpu->mwait. in x86_cpu_realizefn()
9386 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; in x86_cpu_realizefn()
9395 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && in x86_cpu_realizefn()
9396 env->topo_info.threads_per_core > 1) { in x86_cpu_realizefn()
9398 "hyperthreading(%d). Please configure -smp " in x86_cpu_realizefn()
9400 "feature.", env->topo_info.threads_per_core); in x86_cpu_realizefn()
9412 * accel-specific code in cpu_exec_realizefn. in x86_cpu_realizefn()
9414 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in x86_cpu_realizefn()
9415 if (cpu->phys_bits && in x86_cpu_realizefn()
9416 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || in x86_cpu_realizefn()
9417 cpu->phys_bits < 32)) { in x86_cpu_realizefn()
9418 error_setg(errp, "phys-bits should be between 32 and %u " in x86_cpu_realizefn()
9420 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); in x86_cpu_realizefn()
9425 * compat_props or by the host code in host-cpu.c). in x86_cpu_realizefn()
9428 if (cpu->phys_bits == 0) { in x86_cpu_realizefn()
9429 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
9431 if (cpu->guest_phys_bits && in x86_cpu_realizefn()
9432 (cpu->guest_phys_bits > cpu->phys_bits || in x86_cpu_realizefn()
9433 cpu->guest_phys_bits < 32)) { in x86_cpu_realizefn()
9434 error_setg(errp, "guest-phys-bits should be between 32 and %u " in x86_cpu_realizefn()
9436 cpu->phys_bits, cpu->guest_phys_bits); in x86_cpu_realizefn()
9443 if (cpu->phys_bits != 0) { in x86_cpu_realizefn()
9444 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); in x86_cpu_realizefn()
9447 if (cpu->guest_phys_bits != 0) { in x86_cpu_realizefn()
9448 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); in x86_cpu_realizefn()
9452 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { in x86_cpu_realizefn()
9453 cpu->phys_bits = 36; in x86_cpu_realizefn()
9455 cpu->phys_bits = 32; in x86_cpu_realizefn()
9460 if (!cpu->legacy_cache) { in x86_cpu_realizefn()
9462 x86_cpu_get_versioned_cache_info(cpu, xcc->model); in x86_cpu_realizefn()
9464 if (!xcc->model || !cache_info) { in x86_cpu_realizefn()
9467 "CPU model '%s' doesn't support legacy-cache=off", name); in x86_cpu_realizefn()
9470 env->cache_info = *cache_info; in x86_cpu_realizefn()
9473 if (!cpu->consistent_cache) { in x86_cpu_realizefn()
9474 env->enable_legacy_cpuid2_cache = true; in x86_cpu_realizefn()
9477 if (!cpu->vendor_cpuid_only_v2) { in x86_cpu_realizefn()
9478 env->enable_legacy_vendor_cache = true; in x86_cpu_realizefn()
9482 env->cache_info = legacy_amd_cache_info; in x86_cpu_realizefn()
9484 env->cache_info = legacy_intel_cache_info; in x86_cpu_realizefn()
9492 if (mc->smp_props.has_caches) { in x86_cpu_realizefn()
9500 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { in x86_cpu_realizefn()
9521 xcc->parent_realize(dev, &local_err); in x86_cpu_realizefn()
9540 if (cpu->apic_state) { in x86_cpu_unrealizefn()
9541 object_unparent(OBJECT(cpu->apic_state)); in x86_cpu_unrealizefn()
9542 cpu->apic_state = NULL; in x86_cpu_unrealizefn()
9545 xcc->parent_unrealize(dev); in x86_cpu_unrealizefn()
9558 uint64_t f = cpu->env.features[fp->w]; in x86_cpu_get_bit_prop()
9559 bool value = (f & fp->mask) == fp->mask; in x86_cpu_get_bit_prop()
9571 if (dev->realized) { in x86_cpu_set_bit_prop()
9581 cpu->env.features[fp->w] |= fp->mask; in x86_cpu_set_bit_prop()
9583 cpu->env.features[fp->w] &= ~fp->mask; in x86_cpu_set_bit_prop()
9585 cpu->env.user_features[fp->w] |= fp->mask; in x86_cpu_set_bit_prop()
9606 fp = op->opaque; in x86_cpu_register_bit_prop()
9607 assert(fp->w == w); in x86_cpu_register_bit_prop()
9608 fp->mask |= mask; in x86_cpu_register_bit_prop()
9611 fp->w = w; in x86_cpu_register_bit_prop()
9612 fp->mask = mask; in x86_cpu_register_bit_prop()
9625 const char *name = fi->feat_names[bitnr]; in x86_cpu_register_feature_bit_props()
9631 /* Property names should use "-" instead of "_". in x86_cpu_register_feature_bit_props()
9645 if (current_machine && current_machine->cgs) { in x86_cpu_post_initfn()
9647 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); in x86_cpu_post_initfn()
9669 esa->size = 0; in x86_cpu_init_xsave()
9677 CPUX86State *env = &cpu->env; in x86_cpu_init_default_topo()
9679 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; in x86_cpu_init_default_topo()
9682 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); in x86_cpu_init_default_topo()
9683 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); in x86_cpu_init_default_topo()
9684 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); in x86_cpu_init_default_topo()
9691 CPUX86State *env = &cpu->env; in x86_cpu_initfn()
9695 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", in x86_cpu_initfn()
9697 NULL, NULL, (void *)env->features); in x86_cpu_initfn()
9698 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", in x86_cpu_initfn()
9700 NULL, NULL, (void *)cpu->filtered_features); in x86_cpu_initfn()
9704 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); in x86_cpu_initfn()
9705 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); in x86_cpu_initfn()
9707 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); in x86_cpu_initfn()
9710 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); in x86_cpu_initfn()
9711 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); in x86_cpu_initfn()
9712 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); in x86_cpu_initfn()
9713 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); in x86_cpu_initfn()
9714 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); in x86_cpu_initfn()
9715 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); in x86_cpu_initfn()
9716 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); in x86_cpu_initfn()
9717 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); in x86_cpu_initfn()
9718 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); in x86_cpu_initfn()
9719 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); in x86_cpu_initfn()
9720 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); in x86_cpu_initfn()
9721 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); in x86_cpu_initfn()
9722 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); in x86_cpu_initfn()
9723 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); in x86_cpu_initfn()
9724 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); in x86_cpu_initfn()
9725 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); in x86_cpu_initfn()
9726 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); in x86_cpu_initfn()
9727 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); in x86_cpu_initfn()
9728 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); in x86_cpu_initfn()
9729 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); in x86_cpu_initfn()
9730 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); in x86_cpu_initfn()
9734 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); in x86_cpu_initfn()
9735 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; in x86_cpu_initfn()
9736 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); in x86_cpu_initfn()
9738 if (xcc->model) { in x86_cpu_initfn()
9739 x86_cpu_load_model(cpu, xcc->model); in x86_cpu_initfn()
9754 return cpu->apic_id; in x86_cpu_get_arch_id()
9762 return cpu->env.cr[0] & CR0_PG_MASK; in x86_cpu_get_paging_enabled()
9770 cpu->env.eip = value; in x86_cpu_set_pc()
9778 return cpu->env.eip + cpu->env.segs[R_CS].base; in x86_cpu_get_pc()
9785 CPUX86State *env = &cpu->env; in x86_cpu_pending_interrupt()
9794 if (env->hflags2 & HF2_GIF_MASK) { in x86_cpu_pending_interrupt()
9796 !(env->hflags & HF_SMM_MASK)) { in x86_cpu_pending_interrupt()
9799 !(env->hflags2 & HF2_NMI_MASK)) { in x86_cpu_pending_interrupt()
9804 (((env->hflags2 & HF2_VINTR_MASK) && in x86_cpu_pending_interrupt()
9805 (env->hflags2 & HF2_HIF_MASK)) || in x86_cpu_pending_interrupt()
9806 (!(env->hflags2 & HF2_VINTR_MASK) && in x86_cpu_pending_interrupt()
9807 (env->eflags & IF_MASK && in x86_cpu_pending_interrupt()
9808 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { in x86_cpu_pending_interrupt()
9810 } else if (env->hflags2 & HF2_VGIF_MASK) { in x86_cpu_pending_interrupt()
9812 (env->eflags & IF_MASK) && in x86_cpu_pending_interrupt()
9813 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { in x86_cpu_pending_interrupt()
9824 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; in x86_cpu_has_work()
9831 CPUX86State *env = &cpu->env; in x86_disas_set_info()
9833 info->endian = BFD_ENDIAN_LITTLE; in x86_disas_set_info()
9834 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 in x86_disas_set_info()
9835 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 in x86_disas_set_info()
9838 info->cap_arch = CS_ARCH_X86; in x86_disas_set_info()
9839 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 in x86_disas_set_info()
9840 : env->hflags & HF_CS32_MASK ? CS_MODE_32 in x86_disas_set_info()
9842 info->cap_insn_unit = 1; in x86_disas_set_info()
9843 info->cap_insn_split = 8; in x86_disas_set_info()
9855 hflags = env->hflags & HFLAG_COPY_MASK; in x86_update_hflags()
9856 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; in x86_update_hflags()
9857 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); in x86_update_hflags()
9858 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & in x86_update_hflags()
9860 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); in x86_update_hflags()
9862 if (env->cr[4] & CR4_OSFXSR_MASK) { in x86_update_hflags()
9866 if (env->efer & MSR_EFER_LMA) { in x86_update_hflags()
9870 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { in x86_update_hflags()
9873 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> in x86_update_hflags()
9874 (DESC_B_SHIFT - HF_CS32_SHIFT); in x86_update_hflags()
9875 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> in x86_update_hflags()
9876 (DESC_B_SHIFT - HF_SS32_SHIFT); in x86_update_hflags()
9877 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || in x86_update_hflags()
9881 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | in x86_update_hflags()
9882 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; in x86_update_hflags()
9885 env->hflags = hflags; in x86_update_hflags()
9890 /* apic_id = 0 by default for *-user, see commit 9886e834 */
9891 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
9892 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
9893 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
9894 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0),
9895 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
9896 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
9898 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
9899 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
9900 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
9901 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1),
9902 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
9903 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
9905 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9907 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
9909 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
9911 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
9913 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
9915 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
9917 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
9919 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
9921 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
9923 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
9925 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
9927 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
9929 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
9931 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
9933 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
9935 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
9937 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
9939 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
9941 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
9943 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features,
9945 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features,
9947 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
9949 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
9951 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
9954 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
9957 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
9958 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
9961 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
9963 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
9965 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
9967 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
9968 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
9969 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
9973 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
9975 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
9976 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1),
9977 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
9978 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
9979 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
9980 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
9985 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
9986 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
9987 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
9988 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
9989 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
9990 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
9991 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
9992 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
9993 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
9994 DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v2, true),
9995 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true),
9997 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9998 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
10000 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
10001 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
10002 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
10008 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
10009 DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true),
10010 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false),
10011 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
10016 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
10019 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
10025 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
10026 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
10028 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
10030 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true),
10031 DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false),
10033 DEFINE_PROP_BOOL("x-arch-cap-always-on", X86CPU,
10035 DEFINE_PROP_BOOL("x-pdcm-on-even-without-pmu", X86CPU,
10040 #include "hw/core/sysemu-cpu-ops.h"
10066 &xcc->parent_realize); in x86_cpu_common_class_init()
10068 &xcc->parent_unrealize); in x86_cpu_common_class_init()
10072 &xcc->parent_phases); in x86_cpu_common_class_init()
10073 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; in x86_cpu_common_class_init()
10075 cc->class_by_name = x86_cpu_class_by_name; in x86_cpu_common_class_init()
10076 cc->list_cpus = x86_cpu_list; in x86_cpu_common_class_init()
10077 cc->parse_features = x86_cpu_parse_featurestr; in x86_cpu_common_class_init()
10078 cc->dump_state = x86_cpu_dump_state; in x86_cpu_common_class_init()
10079 cc->set_pc = x86_cpu_set_pc; in x86_cpu_common_class_init()
10080 cc->get_pc = x86_cpu_get_pc; in x86_cpu_common_class_init()
10081 cc->gdb_read_register = x86_cpu_gdb_read_register; in x86_cpu_common_class_init()
10082 cc->gdb_write_register = x86_cpu_gdb_write_register; in x86_cpu_common_class_init()
10083 cc->get_arch_id = x86_cpu_get_arch_id; in x86_cpu_common_class_init()
10086 cc->sysemu_ops = &i386_sysemu_ops; in x86_cpu_common_class_init()
10089 cc->tcg_ops = &x86_tcg_ops; in x86_cpu_common_class_init()
10092 cc->gdb_arch_name = x86_gdb_arch_name; in x86_cpu_common_class_init()
10094 cc->gdb_core_xml_file = "i386-64bit.xml"; in x86_cpu_common_class_init()
10096 cc->gdb_core_xml_file = "i386-32bit.xml"; in x86_cpu_common_class_init()
10098 cc->disas_set_info = x86_disas_set_info; in x86_cpu_common_class_init()
10100 dc->user_creatable = true; in x86_cpu_common_class_init()
10114 object_class_property_add_str(oc, "model-id", in x86_cpu_common_class_init()
10117 object_class_property_add(oc, "tsc-frequency", "int", in x86_cpu_common_class_init()
10121 * The "unavailable-features" property has the same semantics as in x86_cpu_common_class_init()
10122 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" in x86_cpu_common_class_init()
10126 object_class_property_add(oc, "unavailable-features", "strList", in x86_cpu_common_class_init()
10131 object_class_property_add(oc, "crash-information", "GuestPanicInformation", in x86_cpu_common_class_init()
10156 /* "base" CPU model, used by query-cpu-model-expansion */
10161 xcc->static_model = true; in x86_cpu_base_class_init()
10162 xcc->migration_safe = true; in x86_cpu_base_class_init()
10163 xcc->model_description = "base CPU model type with no features enabled"; in x86_cpu_base_class_init()
10164 xcc->ordering = 8; in x86_cpu_base_class_init()