Lines Matching refs:Shift

32     "Arithmetic Shift Right by Register", \
39     "Arithmetic Shift Left by Register", \
46     "Logical Shift Right by Register", \
53     "Logical Shift Left by Register", \
78     "Arithmetic Shift Right by Register", \
85     "Arithmetic Shift Left by Register", \
99     "Arithmetic Shift Right by Immediate", \
103     "Logical Shift Right by Immediate", \
107     "Shift Left by Immediate", \
127     "Logical Shift Right by Register", \
130     "Shift Left by Register", \
157        "Shift right with round",
161 Q6INSN(S2_asr_i_p_rnd,"Rdd32=asr(Rss32,#u6):rnd",ATTRIBS(), "Shift right with round",
169 Q6INSN(S4_lsli,"Rd32=lsl(#s6,Rt32)",ATTRIBS(), "Shift an immediate left by register amount",
179     "Shift left by small amount and add",
185 Q6INSN(S4_andi_##TAGEND,"Rx32=and(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)&INNERSEM;})\
186 Q6INSN(S4_ori_##TAGEND, "Rx32=or(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)|INNERSEM;})\
187 Q6INSN(S4_addi_##TAGEND,"Rx32=add(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)+INNERSEM;})\
188 Q6INSN(S4_subi_##TAGEND,"Rx32=sub(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)-INNERSEM;})
520     "Vector Arithmetic Shift Right by Immediate",
530     "Vector Logical Shift Right by Immediate",
539     "Vector Arithmetic Shift Left by Immediate",
550     "Vector Arithmetic Shift Right by Register",
559     "Vector Arithmetic Shift Right by Immediate with Round, Saturate, and Pack",
568     "Vector Arithmetic Shift Right by Immediate with Saturate and Pack",
579     "Vector Arithmetic Shift Right by Immediate with Round",
589     "Vector Arithmetic Shift Left by Register",
600     "Vector Logical Shift Right by Register",
610     "Vector Logical Shift Left by Register",
624     "Vector Arithmetic Shift Right by Immediate",
635     "Vector Arithmetic Shift Right by Immediate with Truncate and Pack",
644     "Vector Arithmetic Shift Right truncate and Pack",
654     "Vector Logical Shift Right by Immediate",
663     "Vector Arithmetic Shift Left by Immediate",
674     "Vector Arithmetic Shift Right by Register",
685     "Vector Arithmetic Shift Left by Register",
695     "Vector Logical Shift Right by Register",
706     "Vector Logical Shift Left by Register",