Lines Matching full:thread

171     (mmvec_current_veclogsize(thread)),
204 warn("aligning misaligned vector. PC=%08x EA=%08x",thread->Regs[REG_PC],(EA));
210 mem_vector_scatter_init(thread, insn, REGION_START, LENGTH, ELEMENT_SIZE);
218 mem_vector_gather_init(thread, insn, REGION_START, LENGTH, ELEMENT_SIZE);
227 mem_vector_scatter_finish(thread, insn, OP);
235 mem_vector_gather_finish(thread, insn);
244 paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
246 FLAG = (pa < (thread->mem_access[slot].paddr+LENGTH));
277 paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
278 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
295 paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
296 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
312 paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
313 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
330 paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
331 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
338 …size1u_t B = sim_mem_read1(thread->system_ptr, thread->threadId, thread->mem_access[slot].paddr+O…
391 if (thread->processor_ptr->arch_proc_options->mmvec_network_addr_log2)
395 paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
415 … dst |= (sim_mem_read1(thread->system_ptr, thread->threadId, mmvecx->vtcm_log.pa[i+j]) << (8*j));
424 …sim_mem_write1(thread->system_ptr,thread->threadId, mmvecx->vtcm_log.pa[i+j], (dst >> (8*j))& 0xFF…
437 paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
438 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
505 …mem_store_release(thread, insn, fVECSIZE(), EA&~(fVECSIZE()-1), EA, TYPE, fUSE_LOOKUP_ADDRESS_BY_R…
513 mem_fetch_vector(thread, insn, EA&~(fVECSIZE()-1), insn->slot, fVECSIZE());
522 thread->last_pkt->double_access_vec = 0;
523 …mem_load_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &DST.ub[0], LEN, fUSE_…
555 thread->last_pkt->double_access_vec = 1;
556 …mem_load_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &DST.ub[size1], …
557 …mem_load_vector_oddva(thread, insn, EA, EA,/* slot */ 0, size1, &DST.ub[0], size1, fUSE_LOOKUP_ADD…
565 thread->last_pkt->pkt_has_vtcm_access = 0;
566 thread->last_pkt->pkt_access_count = 0;
568 thread->last_pkt->pkt_has_vmemu_access = 0;
569 thread->last_pkt->double_access = 0;
573 thread->last_pkt->pkt_has_vmemu_access = 1;
574 thread->last_pkt->double_access = 1;
585 …mem_store_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &SRC.ub[0], 0, 0, fUS…
600 …ore_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &SRC.ub[0], &maskvec.ub[0],…
616 …ore_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &SRC.ub[0], &maskvec.ub[0],…
632 …mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &SRC.ub[size1],…
633 …mem_store_vector_oddva(thread, insn, EA, EA, /* slot */ 0, size1, &SRC.ub[0], 0, 0, fUSE_LOOKUP_AD…
640 thread->last_pkt->pkt_has_vtcm_access = 0;
641 thread->last_pkt->pkt_access_count = 0;
643 thread->last_pkt->double_access = 0;
646 thread->last_pkt->double_access = 1;
647 thread->last_pkt->pkt_has_vmemu_access = 1;
663 …mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(),/* slot */ 1, size2, &SRC.ub[size1], …
664 …mem_store_vector_oddva(thread, insn, EA, /* slot */ 0, size1, &SRC.ub[0], &maskvec.ub[0], 0, fUSE_…
671 thread->last_pkt->pkt_has_vtcm_access = 0;
672 thread->last_pkt->pkt_access_count = 0;
674 thread->last_pkt->double_access = 0;
677 thread->last_pkt->double_access = 1;
678 thread->last_pkt->pkt_has_vmemu_access = 1;
694 …mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &SRC.ub[size1],…
695 …mem_store_vector_oddva(thread, insn, EA, EA, /* slot */ 0, size1, &SRC.ub[0], &maskvec.ub[0], 1, f…
702 thread->last_pkt->pkt_has_vtcm_access = 0;
703 thread->last_pkt->pkt_access_count = 0;
705 thread->last_pkt->double_access = 0;
708 thread->last_pkt->double_access = 1;
709 thread->last_pkt->pkt_has_vmemu_access = 1;
735 mmvec_vtmp_data(thread),