Lines Matching +full:hexagon +full:- +full:linux +full:- +full:user
2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
23 #include "exec/helper-gen.h"
74 if (ctx->need_commit) { in get_result_gpr()
78 if (ctx->new_value[rnum] == NULL) { in get_result_gpr()
79 ctx->new_value[rnum] = tcg_temp_new(); in get_result_gpr()
80 tcg_gen_movi_tl(ctx->new_value[rnum], 0); in get_result_gpr()
82 return ctx->new_value[rnum]; in get_result_gpr()
120 if (ctx->need_commit) { in get_result_pred()
121 if (ctx->new_pred_value[pnum] == NULL) { in get_result_pred()
122 ctx->new_pred_value[pnum] = tcg_temp_new(); in get_result_pred()
123 tcg_gen_movi_tl(ctx->new_pred_value[pnum], 0); in get_result_pred()
125 return ctx->new_pred_value[pnum]; in get_result_pred()
139 * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual in gen_log_pred_write()
145 if (!test_bit(pnum, ctx->pregs_written)) { in gen_log_pred_write()
150 set_bit(pnum, ctx->pregs_written); in gen_log_pred_write()
164 * -> concat the 4 predicate registers together
166 * -> assign from ctx->base.pc_next
168 * -> add current TB changes to existing reg value
176 tcg_gen_movi_tl(dest, ctx->base.pc_next); in gen_read_ctrl_reg()
179 ctx->num_packets); in gen_read_ctrl_reg()
182 ctx->num_insns); in gen_read_ctrl_reg()
185 ctx->num_hvx_insns); in gen_read_ctrl_reg()
198 } else if (reg_num == HEX_REG_PC - 1) { in gen_read_ctrl_reg_pair()
199 TCGv pc = tcg_constant_tl(ctx->base.pc_next); in gen_read_ctrl_reg_pair()
205 ctx->num_packets); in gen_read_ctrl_reg_pair()
207 ctx->num_insns); in gen_read_ctrl_reg_pair()
212 ctx->num_hvx_insns); in gen_read_ctrl_reg_pair()
233 * -> break the value across 4 predicate registers
235 * -> clear the changes
245 ctx->num_packets = 0; in gen_write_ctrl_reg()
248 ctx->num_insns = 0; in gen_write_ctrl_reg()
251 ctx->num_hvx_insns = 0; in gen_write_ctrl_reg()
269 ctx->num_packets = 0; in gen_write_ctrl_reg_pair()
270 ctx->num_insns = 0; in gen_write_ctrl_reg_pair()
273 ctx->num_hvx_insns = 0; in gen_write_ctrl_reg_pair()
357 ctx->mem_idx, MO_32); in gen_store_conditional4()
382 ctx->mem_idx, MO_64); in gen_store_conditional8()
398 int slotval = (ctx->pkt->pkt_has_store_s1 & 1) | (ctx->insn->slot << 1); in gen_slotval()
474 if (ctx->pkt->pkt_has_multi_cof) { in gen_write_new_pc_addr()
477 ctx->branch_taken, tcg_constant_tl(0), in gen_write_new_pc_addr()
479 tcg_gen_movi_tl(ctx->branch_taken, 1); in gen_write_new_pc_addr()
492 target_ulong dest = ctx->pkt->pc + pc_off; in gen_write_new_pc_pcrel()
493 if (ctx->pkt->pkt_has_multi_cof) { in gen_write_new_pc_pcrel()
497 ctx->branch_cond = TCG_COND_ALWAYS; in gen_write_new_pc_pcrel()
499 ctx->branch_cond = cond; in gen_write_new_pc_pcrel()
500 tcg_gen_mov_tl(ctx->branch_taken, pred); in gen_write_new_pc_pcrel()
502 ctx->branch_dest = dest; in gen_write_new_pc_pcrel()
544 gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + riV)); in gen_loop0r()
558 gen_log_reg_write(ctx, HEX_REG_SA1, tcg_constant_tl(ctx->pkt->pc + riV)); in gen_loop1r()
571 gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + riV)); in gen_ploopNsr()
610 if (ctx->insn->part1) { in gen_cmpnd_cmp_jmp()
616 tcg_gen_mov_tl(pred, ctx->new_pred_value[pnum]); in gen_cmpnd_cmp_jmp()
654 gen_cmpnd_cmpi_jmp_t(ctx, pnum, cond, arg, -1, pc_off); in gen_cmpnd_cmp_n1_jmp_t()
660 gen_cmpnd_cmpi_jmp_f(ctx, pnum, cond, arg, -1, pc_off); in gen_cmpnd_cmp_n1_jmp_f()
666 if (ctx->insn->part1) { in gen_cmpnd_tstbit0_jmp()
673 tcg_gen_mov_tl(pred, ctx->new_pred_value[pnum]); in gen_cmpnd_tstbit0_jmp()
699 tcg_gen_movi_tl(lr, ctx->next_PC); in gen_call()
706 tcg_gen_movi_tl(lr, ctx->next_PC); in gen_callr()
719 tcg_gen_movi_tl(lr, ctx->next_PC); in gen_cond_call()
757 Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */ in gen_load_frame()
759 tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_LE | MO_UQ); in gen_load_frame()
766 /* Not modelled in linux-user mode */ in gen_framecheck()
777 tcg_gen_addi_tl(r30, r29, -8); in gen_allocframe()
779 gen_store8(tcg_env, r30, frame, ctx->insn->slot); in gen_allocframe()
830 /* sub-instruction version (no RddV, so handle it manually) */
858 * SET_USR_FIELD(USR_LPCFG, lpcfg - 1); in gen_endloop0()
873 if (!ctx->is_tight_loop) { in gen_endloop0()
877 * LC0--; in gen_endloop0()
896 * LC1--; in gen_endloop1()
932 * SET_USR_FIELD(USR_LPCFG, lpcfg - 1); in gen_endloop01()
945 * LC0--; in gen_endloop01()
948 * LC1--; in gen_endloop01()
1085 * size8u_t mask = ((fCONSTLL(1) << width) - 1); in gen_insert_rp()
1107 /* Possible values for offset are -64 .. 63 */ in gen_insert_rp()
1137 * (fCAST4_8s(fGETWORD(i, RssV)) << -fSXTN(7, 32, RtV))))); in gen_asr_r_svw_trun()
1149 /* Possible values of shift_amt32 are -64 .. 63 */ in gen_asr_r_svw_trun()
1183 if (test_bit(num, ctx->vregs_select)) { in vreg_src_off()
1186 if (test_bit(num, ctx->vregs_updated_tmp)) { in vreg_src_off()
1218 if (ctx->need_commit) { in get_result_qreg()
1230 tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1)); in gen_vreg_load()
1233 tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_LE | MO_UQ); in gen_vreg_load()
1254 ~((int32_t)sizeof(MMVector) - 1)); in gen_vreg_store()
1274 ~((int32_t)sizeof(MMVector) - 1)); in gen_vreg_masked_store()
1323 /* Sets the USR field if `val` is non-zero */ in gen_set_usr_field_if()
1340 TCGv max_val = tcg_constant_tl((1 << (width - 1)) - 1); in gen_sat_i32()
1341 TCGv min_val = tcg_constant_tl(-(1 << (width - 1))); in gen_sat_i32()
1357 TCGv max_val = tcg_constant_tl((1 << width) - 1); in gen_satu_i32()
1374 TCGv_i64 max_val = tcg_constant_i64((1LL << (width - 1)) - 1LL); in gen_sat_i64()
1375 TCGv_i64 min_val = tcg_constant_i64(-(1LL << (width - 1))); in gen_sat_i64()
1394 TCGv_i64 max_val = tcg_constant_i64((1LL << width) - 1LL); in gen_satu_i64()