Lines Matching refs:dc
60 static inline void cris_illegal_insn(DisasContext *dc)
62 qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc);
64 dc->base.is_jmp = DISAS_NORETURN;
67 static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
74 dc->postinc = 0;
75 cris_evaluate_flags(dc);
91 static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
96 if (dc->delayed_branch == 1) {
97 cris_store_direct_jmp(dc);
101 if (dc->flags_x) {
102 gen_store_v10_conditional(dc, addr, val, size, dc->mem_index);
106 tcg_gen_qemu_st_tl(val, addr, dc->mem_index, ctz32(size) | MO_TE);
112 static void cris_set_prefix(DisasContext *dc)
114 dc->clear_prefix = 0;
115 dc->tb_flags |= PFIX_FLAG;
119 dc->clear_x = 0;
120 cris_lock_irq(dc);
123 static void crisv10_prepare_memaddr(DisasContext *dc,
126 if (dc->tb_flags & PFIX_FLAG) {
129 tcg_gen_mov_tl(addr, cpu_R[dc->src]);
133 static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
137 if (dc->tb_flags & PFIX_FLAG) {
138 if (dc->mode == CRISV10_MODE_AUTOINC) {
139 tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
142 if (dc->mode == CRISV10_MODE_AUTOINC) {
143 if (dc->src == 15) {
146 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
153 static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
161 rs = dc->src;
162 is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
164 rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
168 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
172 if (dc->mode == CRISV10_MODE_AUTOINC) {
182 cris_flush_cc_state(dc);
183 crisv10_prepare_memaddr(dc, addr, memsize);
184 gen_load(dc, dst, addr, memsize, 0);
189 insn_len += crisv10_post_memaddr(dc, memsize);
192 if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
193 dc->dst = dc->src;
198 static unsigned int dec10_quick_imm(DisasContext *dc)
205 imm = dc->ir & ((1 << 6) - 1);
208 switch (dc->opcode) {
213 simm = (int8_t)dc->ir;
214 LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
216 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
217 cris_set_prefix(dc);
218 if (dc->dst == 15) {
219 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
221 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
226 LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
228 cris_cc_mask(dc, CC_MASK_NZVC);
230 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
231 cpu_R[dc->dst], c, 4);
234 LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
236 cris_cc_mask(dc, CC_MASK_NZVC);
238 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
239 cpu_R[dc->dst], c, 4);
242 LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
244 cris_cc_mask(dc, CC_MASK_NZVC);
246 cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
247 cpu_R[dc->dst], c, 4);
250 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
252 cris_cc_mask(dc, CC_MASK_NZVC);
254 cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
255 cpu_R[dc->dst], c, 4);
258 LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
260 cris_cc_mask(dc, CC_MASK_NZVC);
265 cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
266 cpu_R[dc->dst], c, 4);
269 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
270 gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
275 LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
282 cris_cc_mask(dc, CC_MASK_NZVC);
284 cris_alu(dc, op, cpu_R[dc->dst],
285 cpu_R[dc->dst], c, 4);
288 LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
290 cris_cc_mask(dc, CC_MASK_NZVC);
292 cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
293 cpu_R[dc->dst], c, 4);
296 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
298 cris_cc_mask(dc, CC_MASK_NZVC);
300 cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
301 cpu_R[dc->dst], c, 4);
308 imm = dc->ir & 0xff;
315 LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
317 cris_cc_mask(dc, 0);
318 cris_prepare_cc_branch(dc, imm, dc->cond);
323 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
324 cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
330 static unsigned int dec10_setclrf(DisasContext *dc)
333 unsigned int set = ~dc->opcode & 1;
335 flags = EXTRACT_FIELD(dc->ir, 0, 3)
336 | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
342 dc->flags_x = X_FLAG;
344 dc->flags_x = 0;
347 cris_evaluate_flags (dc);
348 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
349 cris_update_cc_x(dc);
350 tcg_gen_movi_tl(cc_op, dc->cc_op);
359 dc->flags_uptodate = 1;
360 dc->clear_x = 0;
361 cris_lock_irq(dc);
365 static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
377 static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
383 dec10_reg_prep_sext(dc, size, sext,
384 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
390 assert(dc->dst != 15);
391 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
394 static void dec10_reg_bound(DisasContext *dc, int size)
399 t_gen_zext(t, cpu_R[dc->src], size);
400 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
403 static void dec10_reg_mul(DisasContext *dc, int size, int sext)
410 dec10_reg_prep_sext(dc, size, sext,
411 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
413 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
417 static void dec10_reg_movs(DisasContext *dc)
419 int size = (dc->size & 1) + 1;
422 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
423 cris_cc_mask(dc, CC_MASK_NZVC);
426 if (dc->ir & 32)
427 t_gen_sext(t, cpu_R[dc->src], size);
429 t_gen_zext(t, cpu_R[dc->src], size);
431 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
434 static void dec10_reg_alux(DisasContext *dc, int op)
436 int size = (dc->size & 1) + 1;
439 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
440 cris_cc_mask(dc, CC_MASK_NZVC);
443 if (dc->ir & 32)
444 t_gen_sext(t, cpu_R[dc->src], size);
446 t_gen_zext(t, cpu_R[dc->src], size);
448 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
451 static void dec10_reg_mov_pr(DisasContext *dc)
453 LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
454 cris_lock_irq(dc);
455 if (dc->src == 15) {
456 tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
457 cris_prepare_jmp(dc, JMP_INDIRECT);
460 if (dc->dst == PR_CCS) {
461 cris_evaluate_flags(dc);
463 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
464 cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
467 static void dec10_reg_abs(DisasContext *dc)
471 LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
473 assert(dc->dst != 15);
475 tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
476 tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
477 tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
479 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
482 static void dec10_reg_swap(DisasContext *dc)
486 LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
488 cris_cc_mask(dc, CC_MASK_NZVC);
490 tcg_gen_mov_tl(t0, cpu_R[dc->src]);
491 if (dc->dst & 8)
493 if (dc->dst & 4)
495 if (dc->dst & 2)
497 if (dc->dst & 1)
499 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
502 static void dec10_reg_scc(DisasContext *dc)
504 int cond = dc->dst;
506 LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
508 gen_tst_cc(dc, cpu_R[dc->src], cond);
509 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0);
511 cris_cc_mask(dc, 0);
514 static unsigned int dec10_reg(DisasContext *dc)
518 unsigned int size = dec10_size(dc->size);
521 if (dc->size != 3) {
522 switch (dc->opcode) {
524 LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
525 cris_cc_mask(dc, CC_MASK_NZVC);
526 dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
527 if (dc->dst == 15) {
528 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
529 cris_prepare_jmp(dc, JMP_INDIRECT);
530 dc->delayed_branch = 1;
534 cris_cc_mask(dc, CC_MASK_NZVC);
535 dec10_reg_movs(dc);
538 cris_cc_mask(dc, CC_MASK_NZVC);
539 dec10_reg_alux(dc, CC_OP_ADD);
542 cris_cc_mask(dc, CC_MASK_NZVC);
543 dec10_reg_alux(dc, CC_OP_SUB);
546 LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
547 cris_cc_mask(dc, CC_MASK_NZVC);
548 dec10_reg_alu(dc, CC_OP_ADD, size, 0);
551 LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
552 cris_cc_mask(dc, CC_MASK_NZVC);
553 dec10_reg_alu(dc, CC_OP_SUB, size, 0);
556 LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
557 cris_cc_mask(dc, CC_MASK_NZVC);
558 dec10_reg_alu(dc, CC_OP_CMP, size, 0);
561 LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
562 cris_cc_mask(dc, CC_MASK_NZVC);
563 dec10_reg_bound(dc, size);
566 LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
567 cris_cc_mask(dc, CC_MASK_NZVC);
568 dec10_reg_alu(dc, CC_OP_AND, size, 0);
571 if (dc->src == 15) {
576 LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
577 tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
578 tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
581 LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
582 cris_cc_mask(dc, CC_MASK_NZVC);
583 dec10_reg_alu(dc, CC_OP_LSL, size, 0);
586 LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
587 cris_cc_mask(dc, CC_MASK_NZVC);
588 dec10_reg_alu(dc, CC_OP_LSR, size, 0);
591 LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
592 cris_cc_mask(dc, CC_MASK_NZVC);
593 dec10_reg_alu(dc, CC_OP_ASR, size, 1);
596 LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
597 cris_cc_mask(dc, CC_MASK_NZVC);
598 dec10_reg_alu(dc, CC_OP_OR, size, 0);
601 LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
602 cris_cc_mask(dc, CC_MASK_NZVC);
603 dec10_reg_alu(dc, CC_OP_NEG, size, 0);
606 LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
607 dc->opcode, dc->src, dc->dst, size);
613 cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
618 tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
619 if (dc->src == 15) {
620 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
622 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
624 cris_set_prefix(dc);
628 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
629 dc->opcode, dc->src, dc->dst);
630 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
634 switch (dc->opcode) {
636 cris_cc_mask(dc, CC_MASK_NZVC);
637 dec10_reg_movs(dc);
640 cris_cc_mask(dc, CC_MASK_NZVC);
641 dec10_reg_alux(dc, CC_OP_ADD);
644 cris_cc_mask(dc, CC_MASK_NZVC);
645 dec10_reg_alux(dc, CC_OP_SUB);
648 cris_evaluate_flags(dc);
649 cris_cc_mask(dc, 0);
650 dec10_reg_mov_pr(dc);
653 LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
654 cris_evaluate_flags(dc);
655 if (dc->src != 11) /* fast for srp. */
656 dc->cpustate_changed = 1;
657 t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
661 dec10_setclrf(dc);
664 dec10_reg_swap(dc);
667 cris_cc_mask(dc, CC_MASK_NZVC);
668 dec10_reg_abs(dc);
671 LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
672 cris_cc_mask(dc, CC_MASK_NZVC);
673 dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
676 LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
677 cris_cc_mask(dc, CC_MASK_NZVC);
678 dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
681 LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
682 cris_cc_mask(dc, CC_MASK_NZVC);
683 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
684 gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
685 cpu_R[dc->src], cpu_PR[PR_CCS]);
688 LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
689 cris_cc_mask(dc, CC_MASK_NZVC);
690 cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
691 cpu_R[dc->dst], cpu_R[dc->src], 4);
694 LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
695 cris_evaluate_flags(dc);
696 cris_cc_mask(dc, CC_MASK_NZVC);
697 cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
698 cpu_R[dc->dst], cpu_R[dc->src], 4);
701 dec10_reg_scc(dc);
704 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
705 dc->opcode, dc->src, dc->dst);
706 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
713 static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
720 size, dc->src, dc->dst);
722 cris_cc_mask(dc, CC_MASK_NZVC);
724 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
725 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
726 if (dc->dst == 15) {
727 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
728 cris_prepare_jmp(dc, JMP_INDIRECT);
729 dc->delayed_branch = 1;
735 static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
740 LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
742 crisv10_prepare_memaddr(dc, addr, size);
743 gen_store_v10(dc, addr, cpu_R[dc->dst], size);
744 insn_len += crisv10_post_memaddr(dc, size);
749 static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
751 unsigned int insn_len = 2, rd = dc->dst;
754 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
755 cris_lock_irq(dc);
758 insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
761 cris_prepare_jmp(dc, JMP_INDIRECT);
762 dc->delayed_branch = 1;
765 dc->cpustate_changed = 1;
770 static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
772 unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
775 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
778 crisv10_prepare_memaddr(dc, addr, size);
779 if (dc->dst == PR_CCS) {
781 cris_evaluate_flags(dc);
783 gen_store_v10(dc, addr, t0, size);
785 gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
787 insn_len += crisv10_post_memaddr(dc, size);
788 cris_lock_irq(dc);
793 static void dec10_movem_r_m(DisasContext *dc)
795 int i, pfix = dc->tb_flags & PFIX_FLAG;
799 dc->dst, dc->src, dc->postinc, dc->ir);
803 crisv10_prepare_memaddr(dc, addr, 4);
805 for (i = dc->dst; i >= 0; i--) {
806 if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
807 gen_store_v10(dc, addr, t0, 4);
809 gen_store_v10(dc, addr, cpu_R[i], 4);
814 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
815 tcg_gen_mov_tl(cpu_R[dc->src], t0);
818 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
819 tcg_gen_mov_tl(cpu_R[dc->src], addr);
823 static void dec10_movem_m_r(DisasContext *dc)
825 int i, pfix = dc->tb_flags & PFIX_FLAG;
829 dc->src, dc->dst, dc->postinc, dc->ir);
833 crisv10_prepare_memaddr(dc, addr, 4);
835 for (i = dc->dst; i >= 0; i--) {
836 gen_load(dc, cpu_R[i], addr, 4, 0);
840 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
841 tcg_gen_mov_tl(cpu_R[dc->src], t0);
844 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
845 tcg_gen_mov_tl(cpu_R[dc->src], addr);
849 static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
853 int rd = dc->dst;
857 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
858 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
859 if (dc->dst == 15) {
860 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
861 cris_prepare_jmp(dc, JMP_INDIRECT);
862 dc->delayed_branch = 1;
868 static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
872 int rd = dc->dst;
876 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
877 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
878 if (dc->dst == 15) {
879 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
880 cris_prepare_jmp(dc, JMP_INDIRECT);
881 dc->delayed_branch = 1;
887 static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
889 unsigned int size = (dc->size & 1) ? 2 : 1;
890 unsigned int sx = !!(dc->size & 2);
892 int rd = dc->dst;
895 LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
899 cris_cc_mask(dc, CC_MASK_NZVC);
900 insn_len += dec10_prep_move_m(env, dc, sx, size, t);
901 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
902 if (dc->dst == 15) {
903 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
904 cris_prepare_jmp(dc, JMP_INDIRECT);
905 dc->delayed_branch = 1;
911 static int dec10_dip(CPUCRISState *env, DisasContext *dc)
917 dc->pc, dc->opcode, dc->src, dc->dst);
918 if (dc->src == 15) {
919 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
921 if (dc->postinc) {
926 gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
927 if (dc->postinc)
928 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
931 cris_set_prefix(dc);
935 static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
938 int rd = dc->dst;
941 dc->pc, dc->opcode, dc->src, dc->dst, size);
943 assert(dc->dst != 15);
946 if (!dc->postinc && (dc->ir & (1 << 11))) {
947 int simm = dc->ir & 0xff;
949 /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
953 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
955 cris_set_prefix(dc);
960 insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
962 cris_set_prefix(dc);
966 static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
969 unsigned int size = dec10_size(dc->size);
974 if (dc->size != 3) {
975 switch (dc->opcode) {
977 return dec10_ind_move_m_r(env, dc, size);
979 return dec10_ind_move_r_m(dc, size);
981 LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
982 cris_cc_mask(dc, CC_MASK_NZVC);
983 insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
986 LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
988 cris_evaluate_flags(dc);
989 cris_cc_mask(dc, CC_MASK_NZVC);
991 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
994 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
998 LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
999 cris_cc_mask(dc, CC_MASK_NZVC);
1000 insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
1003 LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
1004 cris_cc_mask(dc, CC_MASK_NZVC);
1005 insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
1008 LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
1009 cris_cc_mask(dc, CC_MASK_NZVC);
1010 insn_len += dec10_ind_bound(env, dc, size);
1013 LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
1014 cris_cc_mask(dc, CC_MASK_NZVC);
1015 insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
1018 LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
1019 cris_cc_mask(dc, CC_MASK_NZVC);
1020 insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
1023 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
1026 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
1029 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
1032 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
1036 LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
1037 cris_cc_mask(dc, CC_MASK_NZVC);
1038 dec10_reg_mul(dc, size, dc->ir & (1 << 10));
1041 insn_len = dec10_bdap_m(env, dc, size);
1059 if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
1061 LOG_DIS("addc op=%d %d\n", dc->src, dc->dst);
1062 cris_cc_mask(dc, CC_MASK_NZVC);
1063 insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);
1068 dc->pc, size, dc->opcode, dc->src, dc->dst);
1069 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
1075 switch (dc->opcode) {
1077 insn_len = dec10_ind_move_m_pr(env, dc);
1080 insn_len = dec10_ind_move_pr_m(dc);
1083 if (dc->src == 15) {
1085 dc->opcode, dc->src, dc->dst);
1086 imm = cris_fetch(env, dc, dc->pc + 2, size, 0);
1087 if (dc->mode == CRISV10_MODE_AUTOINC) {
1090 c = tcg_constant_tl(dc->pc + insn_len);
1091 t_gen_mov_preg_TN(dc, dc->dst, c);
1092 dc->jmp_pc = imm;
1093 cris_prepare_jmp(dc, JMP_DIRECT);
1094 dc->delayed_branch--; /* v10 has no dslot here. */
1096 if (dc->dst == 14) {
1097 LOG_DIS("break %d\n", dc->src);
1098 cris_evaluate_flags(dc);
1099 tcg_gen_movi_tl(env_pc, dc->pc + 2);
1100 c = tcg_constant_tl(dc->src + 2);
1103 dc->base.is_jmp = DISAS_NORETURN;
1107 dc->opcode, dc->src, dc->dst);
1109 c = tcg_constant_tl(dc->pc + insn_len);
1110 t_gen_mov_preg_TN(dc, dc->dst, c);
1111 crisv10_prepare_memaddr(dc, t[0], size);
1112 gen_load(dc, env_btarget, t[0], 4, 0);
1113 insn_len += crisv10_post_memaddr(dc, size);
1114 cris_prepare_jmp(dc, JMP_INDIRECT);
1115 dc->delayed_branch--; /* v10 has no dslot here. */
1121 dc->pc, dc->opcode, dc->dst, dc->src);
1122 dec10_movem_r_m(dc);
1125 LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
1126 dec10_movem_m_r(dc);
1130 dc->pc, dc->opcode, dc->dst, dc->src);
1131 tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
1132 c = tcg_constant_tl(dc->pc + insn_len);
1133 t_gen_mov_preg_TN(dc, dc->dst, c);
1134 cris_prepare_jmp(dc, JMP_INDIRECT);
1135 dc->delayed_branch--; /* v10 has no dslot here. */
1138 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
1141 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
1144 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
1147 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
1150 insn_len = dec10_dip(env, dc);
1154 cris_cc_mask(dc, 0);
1155 simm = cris_fetch(env, dc, dc->pc + 2, 2, 1);
1158 LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
1159 cris_prepare_cc_branch(dc, simm, dc->cond);
1163 LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
1164 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
1171 static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
1176 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
1179 dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
1180 dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
1181 dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
1182 dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
1183 dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
1184 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
1186 dc->clear_prefix = 1;
1189 if (dc->src == 15 || dc->dst == 15)
1190 tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
1192 switch (dc->mode) {
1194 insn_len = dec10_quick_imm(dc);
1197 insn_len = dec10_reg(dc);
1201 insn_len = dec10_ind(env, dc);
1205 if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
1206 dc->tb_flags &= ~PFIX_FLAG;
1208 if (dc->tb_flags != dc->base.tb->flags) {
1209 dc->cpustate_changed = 1;
1214 if (dc->delayed_branch == 2) {
1215 cris_lock_irq(dc);