arm/tcg/translate.h

5 #include "tcg/tcg-op.h"
6 #include "tcg/tcg-op-gvec.h"
8 #include "exec/translation-block.h"
9 #include "exec/helper-gen.h"
11 #include "cpu-features.h"
38      * needed to bring cpu_pc current: pc_curr - pc_save.
40      * pc_save contains -1 to indicate that relative updates are no
50     /* Thumb-2 conditional execution bits.  */
53     /* M-profile ECI/ICI exception-continuable instruction state */
69     bool ns;        /* Use non-secure CPREG bank on access */
98      * information from traps due to FP being disabled, we can't do a single
99      * "is fp access disabled" check at a high level in the decode tree.
105      *  -1: checked, access denied
109     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
110      * single-step support).
114     /* True if the insn just emitted was a load-exclusive instruction
121     /* True if v8.3-PAuth is active.  */
123     /* True if v8.5-MTE access to tags is enabled; index with is_unpriv.  */
125     /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv.  */
127     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
139     /* True if non-streaming insns should raise an SME Streaming exception. */
141     /* True if the current instruction is non-streaming. */
145     /* True if fine-grained traps are active */
147     /* True if fine-grained trap on SVC is enabled */
161     /* True if NV2 enabled and NV2 RAM accesses are big-endian */
165     /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */
168      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
172     /* A copy of cpu->dcz_blocksize. */
174     /* A copy of cpu->gm_blocksize. */
189 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
200     return -x;  in negate()
245     return 64 - x;  in rsub_64()
250     return 32 - x;  in rsub_32()
255     return 16 - x;  in rsub_16()
260     return 8 - x;  in rsub_8()
276     return MO_32 - x;  in neon_3same_fp_size()
281     return (dc->features & (1ULL << feature)) != 0;  in arm_dc_feature()
286     return arm_to_core_mmu_idx(s->mmu_idx);  in get_mem_index()
298     assert(!s->insn_start_updated);  in disas_set_insn_syndrome()
299     s->insn_start_updated = true;  in disas_set_insn_syndrome()
300     tcg_set_insn_start_param(s->base.insn_start, 2, syn);  in disas_set_insn_syndrome()
305     return s->base.pc_next - s->pc_curr;  in curr_insn_len()
314  * WFI also needs special handling when single-stepping.
324  * custom end-of-TB code)
363 /* Return state of Alternate Half-precision flag, caller frees result */
398 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
401     if (s->ss_active) {  in gen_ss_advance()
402         s->pstate_ss = 0;  in gen_ss_advance()
636     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
683     return (CPUARMTBFlags){ tb->flags, tb->cs_base };  in arm_tbflags_from_tb()
708  * Build the complete MemOp for a memory operation, including alignment,
721     if (s->align_mem && !(opc & MO_AMASK)) {  in finalize_memop_atom()
724     return opc | atom | s->be_data;  in finalize_memop_atom()
736     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN;  in finalize_memop()
750     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR;  in finalize_memop_pair()
766      * the pair of 64-bit accesses.  If !IsAligned(8), the middle cases  in finalize_memop_asimd()
786  * callers must catch this; we return the 64-bit constant value defined
803         .pc_save = s->pc_save,  in gen_disas_label()
814     s->pc_save = l.pc_save;  in set_disas_label()
855         s->is_nonstreaming = true;                                \