2683                                      int *tgtmode, int *regno)  in msr_banked_access_decode()  argument
2723             *tgtmode = ARM_CPU_MODE_FIQ;  in msr_banked_access_decode()
2726             *tgtmode = ARM_CPU_MODE_IRQ;  in msr_banked_access_decode()
2729             *tgtmode = ARM_CPU_MODE_SVC;  in msr_banked_access_decode()
2732             *tgtmode = ARM_CPU_MODE_ABT;  in msr_banked_access_decode()
2735             *tgtmode = ARM_CPU_MODE_UND;  in msr_banked_access_decode()
2738             *tgtmode = ARM_CPU_MODE_MON;  in msr_banked_access_decode()
2741             *tgtmode = ARM_CPU_MODE_HYP;  in msr_banked_access_decode()
2752             *tgtmode = ARM_CPU_MODE_USR;  in msr_banked_access_decode()
2756             *tgtmode = ARM_CPU_MODE_FIQ;  in msr_banked_access_decode()
2760             *tgtmode = ARM_CPU_MODE_IRQ;  in msr_banked_access_decode()
2764             *tgtmode = ARM_CPU_MODE_SVC;  in msr_banked_access_decode()
2768             *tgtmode = ARM_CPU_MODE_ABT;  in msr_banked_access_decode()
2772             *tgtmode = ARM_CPU_MODE_UND;  in msr_banked_access_decode()
2776             *tgtmode = ARM_CPU_MODE_MON;  in msr_banked_access_decode()
2780             *tgtmode = ARM_CPU_MODE_HYP;  in msr_banked_access_decode()
2792     switch (*tgtmode) {  in msr_banked_access_decode()
2853     int tgtmode = 0, regno = 0;  in gen_msr_banked()  local
2855     if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {  in gen_msr_banked()
2864                           tcg_constant_i32(tgtmode),  in gen_msr_banked()
2872     int tgtmode = 0, regno = 0;  in gen_mrs_banked()  local
2874     if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {  in gen_mrs_banked()
2883                           tcg_constant_i32(tgtmode),  in gen_mrs_banked()