Lines Matching refs:tmp1
407 TCGv_i32 tmp1 = tcg_temp_new_i32(); in gen_smul_dual() local
409 tcg_gen_ext16s_i32(tmp1, a); in gen_smul_dual()
411 tcg_gen_mul_i32(tmp1, tmp1, tmp2); in gen_smul_dual()
415 tcg_gen_mov_i32(a, tmp1); in gen_smul_dual()
540 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
542 tcg_gen_andi_i32(tmp1, t1, 0x1f); \
543 tcg_gen_##name##_i32(tmpd, t0, tmp1); \
544 tcg_gen_andi_i32(tmp1, t1, 0xe0); \
545 tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \
553 TCGv_i32 tmp1 = tcg_temp_new_i32(); in GEN_SHIFT() local
555 tcg_gen_andi_i32(tmp1, t1, 0xff); in GEN_SHIFT()
556 tcg_gen_umin_i32(tmp1, tmp1, tcg_constant_i32(31)); in GEN_SHIFT()
557 tcg_gen_sar_i32(dest, t0, tmp1); in GEN_SHIFT()
3706 TCGv_i32 tmp1, tmp2; in op_s_rrr_shi() local
3710 tmp1 = load_reg(s, a->rn); in op_s_rrr_shi()
3712 gen(tmp1, tmp1, tmp2); in op_s_rrr_shi()
3715 gen_logic_CC(tmp1); in op_s_rrr_shi()
3717 return store_reg_kind(s, a->rd, tmp1, kind); in op_s_rrr_shi()
3746 TCGv_i32 tmp1, tmp2; in op_s_rrr_shr() local
3748 tmp1 = load_reg(s, a->rs); in op_s_rrr_shr()
3750 gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); in op_s_rrr_shr()
3751 tmp1 = load_reg(s, a->rn); in op_s_rrr_shr()
3753 gen(tmp1, tmp1, tmp2); in op_s_rrr_shr()
3756 gen_logic_CC(tmp1); in op_s_rrr_shr()
3758 return store_reg_kind(s, a->rd, tmp1, kind); in op_s_rrr_shr()
3765 TCGv_i32 tmp1, tmp2; in op_s_rxr_shr() local
3767 tmp1 = load_reg(s, a->rs); in op_s_rxr_shr()
3769 gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); in op_s_rxr_shr()
3792 TCGv_i32 tmp1; in op_s_rri_rot() local
3799 tmp1 = load_reg(s, a->rn); in op_s_rri_rot()
3801 gen(tmp1, tmp1, tcg_constant_i32(imm)); in op_s_rri_rot()
3804 gen_logic_CC(tmp1); in op_s_rri_rot()
3806 return store_reg_kind(s, a->rd, tmp1, kind); in op_s_rri_rot()