226      *  if PL2, UNPREDICTABLE (we choose to implement as if PL0)  in get_a32_user_mem_index()
234     case ARMMMUIdx_E2:        /* this one is UNPREDICTABLE */  in get_a32_user_mem_index()
309          * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]  in store_reg()
848      *  - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE  in gen_bxns()
851      *    is correct in the non-UNPREDICTABLE cases, and we can choose  in gen_bxns()
852      *    "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.  in gen_bxns()
2687      * unpredictable cases.  in msr_banked_access_decode()
2688      * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:  in msr_banked_access_decode()
2826          * and UNPREDICTABLE if accessed from anything except Monitor  in msr_banked_access_decode()
3393      * - UNPREDICTABLE in User or System mode  in gen_srs()
3394      * - UNPREDICTABLE if the specified mode is:  in gen_srs()
3399      * For the UNPREDICTABLE cases we choose to UNDEF.  in gen_srs()
3886                  * In User mode, UNPREDICTABLE; we choose UNDEF.  in DO_CMP2()
3908                  * In User mode, UNPREDICTABLE; we choose UNDEF.
3985         /* Decode falls through to ORR/MOV UNPREDICTABLE handling */  in do_mve_shl_ri()
3995         /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */  in do_mve_shl_ri()
4070         /* Decode falls through to ORR/MOV UNPREDICTABLE handling */  in do_mve_shl_rr()
4081         /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */  in do_mve_shl_rr()
4135         /* Decode falls through to ORR/MOV UNPREDICTABLE handling */  in do_mve_sh_ri()
4141         /* These rda cases are UNPREDICTABLE; we choose to UNDEF */  in do_mve_sh_ri()
4187         /* Decode falls through to ORR/MOV UNPREDICTABLE handling */  in do_mve_sh_rr()
4194         /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */  in do_mve_sh_rr()
4886         /* We UNDEF for these UNPREDICTABLE cases */  in trans_TT()
4990      * is either UNPREDICTABLE or has defined behaviour  in op_store_rr()
5137      * is either UNPREDICTABLE or has defined behaviour  in op_store_ri()
5295     /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */  in op_strex()
5298     /* We UNDEF for these UNPREDICTABLE cases.  */  in op_strex()
5335     /* We UNDEF for these UNPREDICTABLE cases.  */  in trans_STREXD_a32()
5378     /* We UNDEF for these UNPREDICTABLE cases.  */  in trans_STLEXD_a32()
5418     /* We UNDEF for these UNPREDICTABLE cases.  */  in op_stl()
5451     /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */  in op_ldrex()
5454     /* We UNDEF for these UNPREDICTABLE cases.  */  in op_ldrex()
5489     /* We UNDEF for these UNPREDICTABLE cases.  */  in trans_LDREXD_a32()
5532     /* We UNDEF for these UNPREDICTABLE cases.  */  in trans_LDAEXD_a32()
5572     /* We UNDEF for these UNPREDICTABLE cases.  */  in op_lda()
5636         /* UNPREDICTABLE; we choose to UNDEF */  in op_bfx()
5671         /* UNPREDICTABLE; we choose to UNDEF */  in trans_BFCI()
6318      * This is UNPREDICTABLE for n < 1 in all encodings, and we choose  in op_stm()
6319      * to UNDEF. In the T32 STM encoding n == 1 is also UNPREDICTABLE,  in op_stm()
6365     /* Writeback register in register list is UNPREDICTABLE for T32.  */  in trans_STM_t32()
6403      * This is UNPREDICTABLE for n < 1 in all encodings, and we choose  in do_ldm()
6404      * to UNDEF. In the T32 LDM encoding n == 1 is also UNPREDICTABLE,  in do_ldm()
6467      * Writeback register in register list is UNPREDICTABLE  in trans_LDM_a32()
6480     /* Writeback register in register list is UNPREDICTABLE for T32. */  in trans_LDM_t32()
6509         /* UNPREDICTABLE; we choose to UNDEF */  in trans_CLRM()
6652          * CONSTRAINED UNPREDICTABLE: we choose to UNDEF  in trans_DLS()
6691          * CONSTRAINED UNPREDICTABLE: we choose to UNDEF  in trans_WLS()
6697          * WLS in an IT block is CONSTRAINED UNPREDICTABLE;  in trans_WLS()
6772          * LE in an IT block is CONSTRAINED UNPREDICTABLE;  in trans_LE()
7049     /* TODO: There are quite a lot of UNPREDICTABLE argument combinations. */  in trans_CPS()
7205      * condition are UNPREDICTABLE; we take the CONSTRAINED  in trans_IT()
7206      * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110,  in trans_IT()
7230         /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */  in trans_CSEL()
7297         /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we  in disas_arm_insn()
7791      * A larger class of instructions are UNPREDICTABLE if used  in thumb_insn_is_unconditional()
7794      * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE  in thumb_insn_is_unconditional()