Lines Matching refs:rn
346 static void check_lse2_align(DisasContext *s, int rn, int imm, in check_lse2_align() argument
356 tcg_gen_extrl_i64_i32(tmp, cpu_reg_sp(s, rn)); in check_lse2_align()
365 tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm); in check_lse2_align()
377 static MemOp check_atomic_align(DisasContext *s, int rn, MemOp mop) in check_atomic_align() argument
395 check_lse2_align(s, rn, 0, true, mop); in check_atomic_align()
403 static MemOp check_ordered_align(DisasContext *s, int rn, int imm, in check_ordered_align() argument
418 check_lse2_align(s, rn, imm, is_write, mop); in check_ordered_align()
660 static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, in gen_gvec_fn2() argument
663 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), in gen_gvec_fn2()
670 static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn, in gen_gvec_fn2i() argument
673 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), in gen_gvec_fn2i()
678 static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm, in gen_gvec_fn3() argument
681 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), in gen_gvec_fn3()
686 static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, in gen_gvec_fn4() argument
689 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), in gen_gvec_fn4()
696 int rn, int data, gen_helper_gvec_2 *fn) in gen_gvec_op2_ool() argument
699 vec_full_reg_offset(s, rn), in gen_gvec_op2_ool()
705 int rn, int rm, int data, gen_helper_gvec_3 *fn) in gen_gvec_op3_ool() argument
708 vec_full_reg_offset(s, rn), in gen_gvec_op3_ool()
716 static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, in gen_gvec_op3_fpst() argument
722 vec_full_reg_offset(s, rn), in gen_gvec_op3_fpst()
728 static void gen_gvec_op4_ool(DisasContext *s, bool is_q, int rd, int rn, in gen_gvec_op4_ool() argument
732 vec_full_reg_offset(s, rn), in gen_gvec_op4_ool()
742 static void gen_gvec_op4_fpst(DisasContext *s, bool is_q, int rd, int rn, in gen_gvec_op4_fpst() argument
748 vec_full_reg_offset(s, rn), in gen_gvec_op4_fpst()
1314 gen_gvec_op2_ool(s, a->q, a->rd, a->rn, data, fn); in do_gvec_op2_ool()
1326 gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, data, fn); in do_gvec_op3_ool()
1337 gen_gvec_fn3(s, a->q, a->rd, a->rn, a->rm, fn, a->esz); in do_gvec_fn3()
1348 gen_gvec_fn3(s, a->q, a->rd, a->rn, a->rm, fn, a->esz); in do_gvec_fn3_no64()
1367 gen_gvec_fn4(s, a->q, a->rd, a->rn, a->rm, a->ra, fn, a->esz); in do_gvec_fn4()
1506 static void set_btype_for_br(DisasContext *s, int rn) in set_btype_for_br() argument
1510 if (rn == 16 || rn == 17) { in set_btype_for_br()
1531 set_btype_for_br(s, a->rn); in trans_BR()
1532 gen_a64_set_pc(s, cpu_reg(s, a->rn)); in trans_BR()
1539 TCGv_i64 dst = cpu_reg(s, a->rn); in trans_BLR()
1555 gen_a64_set_pc(s, cpu_reg(s, a->rn)); in trans_RET()
1590 dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); in trans_BRAZ()
1591 set_btype_for_br(s, a->rn); in trans_BRAZ()
1605 dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); in trans_BLRAZ()
1636 dst = auth_branch_target(s, cpu_reg(s,a->rn), cpu_reg_sp(s, a->rm), !a->m); in trans_BRA()
1638 set_btype_for_br(s, a->rn); in trans_BRA()
1650 dst = auth_branch_target(s, cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm), !a->m); in trans_BLRA()
2664 static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn, in gen_load_exclusive() argument
2669 MemOp memop = check_atomic_align(s, rn, size + is_pair); in gen_load_exclusive()
2672 dirty_addr = cpu_reg_sp(s, rn); in gen_load_exclusive()
2673 clean_addr = gen_mte_check1(s, dirty_addr, false, rn != 31, memop); in gen_load_exclusive()
2710 int rn, int size, int is_pair) in gen_store_exclusive() argument
2738 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); in gen_store_exclusive()
2765 gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_store_exclusive()
2826 int rn, int size) in gen_compare_and_swap() argument
2834 if (rn == 31) { in gen_compare_and_swap()
2837 memop = check_atomic_align(s, rn, size); in gen_compare_and_swap()
2838 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_compare_and_swap()
2844 int rn, int size) in gen_compare_and_swap_pair() argument
2854 if (rn == 31) { in gen_compare_and_swap_pair()
2859 memop = check_atomic_align(s, rn, size + 1); in gen_compare_and_swap_pair()
2860 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_compare_and_swap_pair()
2927 if (a->rn == 31) { in trans_STXR()
2933 gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false); in trans_STXR()
2939 if (a->rn == 31) { in trans_LDXR()
2942 gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, false); in trans_LDXR()
2963 if (a->rn == 31) { in trans_STLR()
2967 memop = check_ordered_align(s, a->rn, 0, true, a->sz); in trans_STLR()
2968 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), in trans_STLR()
2969 true, a->rn != 31, memop); in trans_STLR()
2986 if (a->rn == 31) { in trans_LDAR()
2989 memop = check_ordered_align(s, a->rn, 0, false, a->sz); in trans_LDAR()
2990 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), in trans_LDAR()
2991 false, a->rn != 31, memop); in trans_LDAR()
3000 if (a->rn == 31) { in trans_STXP()
3006 gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, true); in trans_STXP()
3012 if (a->rn == 31) { in trans_LDXP()
3015 gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, true); in trans_LDXP()
3031 gen_compare_and_swap_pair(s, a->rs, a->rt, a->rn, a->sz); in trans_CASP()
3040 gen_compare_and_swap(s, a->rs, a->rt, a->rn, a->sz); in trans_CAS()
3077 if (a->rn == 31) { in op_addr_ldstpair_pre()
3081 *dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in op_addr_ldstpair_pre()
3087 (a->w || a->rn != 31), 2 << a->sz, mop); in op_addr_ldstpair_pre()
3097 tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); in op_addr_ldstpair_post()
3256 if (a->rn == 31) { in trans_STGP()
3260 dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in trans_STGP()
3304 if (a->rn == 31) { in op_addr_ldst_imm_pre()
3308 *dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in op_addr_ldst_imm_pre()
3314 a->w || a->rn != 31, in op_addr_ldst_imm_pre()
3325 tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); in op_addr_ldst_imm_post()
3401 if (a->rn == 31) { in op_addr_ldst_pre()
3404 *dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in op_addr_ldst_pre()
3493 if (a->rn == 31) { in do_atomic_ld()
3496 mop = check_atomic_align(s, a->rn, mop); in do_atomic_ld()
3497 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, in do_atomic_ld()
3498 a->rn != 31, mop); in do_atomic_ld()
3550 if (a->rn == 31) { in TRANS_FEAT()
3553 mop = check_ordered_align(s, a->rn, 0, false, a->sz); in TRANS_FEAT()
3554 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, in TRANS_FEAT()
3555 a->rn != 31, mop); in TRANS_FEAT()
3579 if (a->rn == 31) { in trans_LDRA()
3582 dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in trans_LDRA()
3600 a->w || a->rn != 31, memop); in trans_LDRA()
3608 tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); in trans_LDRA()
3623 if (a->rn == 31) { in trans_LDAPR_i()
3627 mop = check_ordered_align(s, a->rn, a->imm, false, mop); in trans_LDAPR_i()
3628 dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in trans_LDAPR_i()
3654 if (a->rn == 31) { in trans_STLR_i()
3658 mop = check_ordered_align(s, a->rn, a->imm, true, mop); in trans_STLR_i()
3659 dirty_addr = read_cpu_reg_sp(s, a->rn, 1); in trans_STLR_i()
3690 if (a->rn == 31) { in trans_LD_mult()
3701 tcg_rn = cpu_reg_sp(s, a->rn); in trans_LD_mult()
3707 clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, total, in trans_LD_mult()
3781 if (a->rn == 31) { in trans_ST_mult()
3792 tcg_rn = cpu_reg_sp(s, a->rn); in trans_ST_mult()
3798 clean_addr = gen_mte_checkN(s, tcg_rn, true, a->p || a->rn != 31, total, in trans_ST_mult()
3852 if (a->rn == 31) { in trans_ST_single()
3857 tcg_rn = cpu_reg_sp(s, a->rn); in trans_ST_single()
3860 clean_addr = gen_mte_checkN(s, tcg_rn, true, a->p || a->rn != 31, in trans_ST_single()
3892 if (a->rn == 31) { in trans_LD_single()
3897 tcg_rn = cpu_reg_sp(s, a->rn); in trans_LD_single()
3900 clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, in trans_LD_single()
3932 if (a->rn == 31) { in trans_LD_single_repl()
3937 tcg_rn = cpu_reg_sp(s, a->rn); in trans_LD_single_repl()
3940 clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, in trans_LD_single_repl()
3976 if (a->rn == 31) { in trans_STZGM()
3980 addr = read_cpu_reg_sp(s, a->rn, true); in trans_STZGM()
4008 if (a->rn == 31) { in trans_STGM()
4012 addr = read_cpu_reg_sp(s, a->rn, true); in trans_STGM()
4040 if (a->rn == 31) { in trans_LDGM()
4044 addr = read_cpu_reg_sp(s, a->rn, true); in trans_LDGM()
4071 if (a->rn == 31) { in trans_LDG()
4075 addr = read_cpu_reg_sp(s, a->rn, true); in trans_LDG()
4101 tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); in trans_LDG()
4110 if (a->rn == 31) { in do_STG()
4114 addr = read_cpu_reg_sp(s, a->rn, true); in do_STG()
4168 tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); in do_STG()
4195 if (a->rs == a->rn || a->rs == a->rd || a->rn == a->rd || in do_SET()
4196 a->rd == 31 || a->rn == 31) { in do_SET()
4207 is_epilogue, false, true, a->rd, a->rs, a->rn); in do_SET()
4249 if (a->rs == a->rn || a->rs == a->rd || a->rn == a->rd || in do_CPY()
4250 a->rd == 31 || a->rs == 31 || a->rn == 31) { in do_CPY()
4262 false, true, a->rd, a->rs, a->rn); in do_CPY()
4300 TCGv_i64 tcg_rn = rn_sp ? cpu_reg_sp(s, a->rn) : cpu_reg(s, a->rn); in gen_rri()
4354 tcg_rn = cpu_reg_sp(s, a->rn); in gen_add_sub_imm_with_tags()
4473 tcg_rn = cpu_reg(s, a->rn); in gen_rri_log()
4535 TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); in trans_SBFM()
4575 TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); in trans_UBFM()
4582 tcg_tmp = read_cpu_reg(s, a->rn, 1); in trans_UBFM()
4600 TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); in trans_BFM()
4607 tcg_tmp = read_cpu_reg(s, a->rn, 1); in trans_BFM()
4645 tcg_rn = cpu_reg(s, a->rn); in trans_EXTR()
4654 if (a->rm == a->rn) { in trans_EXTR()
4715 read_vec_element_i32(s, tcg_op1, a->rn, 3, MO_32); in TRANS_FEAT()
4736 gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->imm, fn); in do_crypto3i()
4752 vec_full_reg_offset(s, a->rn), in TRANS_FEAT()
4788 read_vec_element(s, tmp, a->rn, idx, esz); in trans_DUP_element_s()
4807 vec_reg_offset(s, a->rn, idx, esz), in trans_DUP_element_v()
4827 cpu_reg(s, a->rn)); in trans_DUP_general()
4851 read_vec_element(s, tcg_rd, a->rn, idx, esz | is_signed); in do_smov_umov()
4871 write_vec_element(s, cpu_reg(s, a->rn), a->rd, idx, esz); in TRANS()
4889 read_vec_element(s, tmp, a->rn, sidx, esz); in trans_INS_element()
4913 TCGv_i64 t0 = read_fp_dreg(s, a->rn); in do_fp3_scalar()
4921 TCGv_i32 t0 = read_fp_sreg(s, a->rn); in do_fp3_scalar()
4932 TCGv_i32 t0 = read_fp_hreg(s, a->rn); in do_fp3_scalar()
5122 read_vec_element(s, t1, a->rn, 0, esz | sgn_n); in do_satacc_s()
5152 read_vec_element(s, t0, a->rn, 0, MO_64); in TRANS()
5178 TCGv_i64 t0 = read_fp_dreg(s, a->rn); in do_env_scalar2()
5186 read_vec_element_i32(s, t0, a->rn, 0, a->esz); in do_env_scalar2()
5264 read_vec_element_i32(s, t0, a->rn, 0, a->esz); in do_env_scalar3_hs()
5285 TCGv_i64 t0 = read_fp_dreg(s, a->rn); in do_cmop_d()
5322 gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm, in TRANS()
5501 vec_full_reg_offset(s, a->rn), in do_fmlal()
5534 TRANS(BSL_v, do_bitsel, a->q, a->rd, a->rd, a->rn, a->rm)
5535 TRANS(BIT_v, do_bitsel, a->q, a->rd, a->rm, a->rn, a->rd)
5536 TRANS(BIF_v, do_bitsel, a->q, a->rd, a->rm, a->rd, a->rn)
5583 vec_full_reg_offset(s, a->rn), in TRANS()
5606 gen_gvec_op4_ool(s, a->q, a->rd, a->rn, a->rm, a->rd, 0, fn); in TRANS()
5627 gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, false, a->q, in TRANS_FEAT()
5668 gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, in trans_FCMLA_v()
5689 int rd, int rn, int rm, int idx, in do_3op_widening() argument
5723 read_vec_element(s, tcg_op1, rn, elt + top_half, memop); in do_3op_widening()
5752 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5755 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5758 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5761 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5764 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5767 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5771 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
5774 a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
5777 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
5780 a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
5783 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
5786 a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
5824 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5827 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5830 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5833 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5836 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5839 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5842 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5845 a->esz, a->q, a->rd, a->rn, a->rm, -1,
5899 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5902 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5905 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
5909 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
5912 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
5915 a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
5942 read_vec_element(s, tcg_op0, a->rn, elt, esz + 1); in do_addsub_wide()
5992 read_vec_element(s, tcg_op0, a->rn, elt, esz + 1); in TRANS()
6017 gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->q, fn); in TRANS()
6034 TCGv_i64 t0 = read_fp_dreg(s, a->rn); in TRANS()
6044 TCGv_i32 t0 = read_fp_sreg(s, a->rn); in TRANS()
6057 TCGv_i32 t0 = read_fp_hreg(s, a->rn); in TRANS()
6080 TCGv_i64 t1 = read_fp_dreg(s, a->rn); in do_fmla_scalar_idx()
6094 TCGv_i32 t1 = read_fp_sreg(s, a->rn); in do_fmla_scalar_idx()
6111 TCGv_i32 t1 = read_fp_hreg(s, a->rn); in do_fmla_scalar_idx()
6142 read_vec_element_i32(s, t0, a->rn, 0, a->esz); in TRANS()
6164 read_vec_element_i32(s, t0, a->rn, 0, a->esz); in do_env_scalar3_idx_hs()
6188 read_vec_element(s, t1, a->rn, 0, a->esz | MO_SIGN); in do_scalar_muladd_widening_idx()
6230 gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm, in do_fp3_vector_idx()
6276 gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, in TRANS()
6291 vec_full_reg_offset(s, a->rn), in TRANS()
6309 gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, a->idx, fns[a->esz - 1]); in TRANS_FEAT()
6329 gen_gvec_op4_ool(s, a->q, a->rd, a->rn, a->rm, a->rd, in TRANS()
6344 vec_full_reg_offset(s, a->rn), in TRANS()
6383 gen_gvec_op4_ool(s, a->q, a->rd, a->rn, a->rm, a->rd, a->idx, fn); in TRANS_FEAT()
6404 gen_gvec_op4_fpst(s, true, a->rd, a->rn, a->rm, a->rd, 0, in TRANS_FEAT()
6432 gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd, in trans_FCMLA_vi()
6450 read_vec_element(s, t0, a->rn, 0, MO_64); in do_fp3_scalar_pair()
6451 read_vec_element(s, t1, a->rn, 1, MO_64); in do_fp3_scalar_pair()
6461 read_vec_element_i32(s, t0, a->rn, 0, MO_32); in do_fp3_scalar_pair()
6462 read_vec_element_i32(s, t1, a->rn, 1, MO_32); in do_fp3_scalar_pair()
6475 read_vec_element_i32(s, t0, a->rn, 0, MO_16); in do_fp3_scalar_pair()
6476 read_vec_element_i32(s, t1, a->rn, 1, MO_16); in do_fp3_scalar_pair()
6499 read_vec_element(s, t0, a->rn, 0, MO_64); in trans_ADDP_s()
6500 read_vec_element(s, t1, a->rn, 1, MO_64); in trans_ADDP_s()
6536 read_vec_element(s, t_true, a->rn, 0, a->esz); in trans_FCSEL()
6567 TCGv_i64 tn = read_fp_dreg(s, a->rn); in do_fmadd()
6585 TCGv_i32 tn = read_fp_sreg(s, a->rn); in do_fmadd()
6606 TCGv_i32 tn = read_fp_hreg(s, a->rn); in do_fmadd()
6702 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; in disas_logic_reg() local
6710 rn = extract32(insn, 5, 5); in disas_logic_reg()
6720 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { in disas_logic_reg()
6746 tcg_rn = cpu_reg(s, rn); in disas_logic_reg()
6803 int rn = extract32(insn, 5, 5); in disas_add_sub_ext_reg() local
6827 tcg_rn = read_cpu_reg_sp(s, rn, sf); in disas_add_sub_ext_reg()
6872 int rn = extract32(insn, 5, 5); in disas_add_sub_reg() local
6889 tcg_rn = read_cpu_reg(s, rn, sf); in disas_add_sub_reg()
6927 int rn = extract32(insn, 5, 5); in disas_data_proc_3src() local
6964 TCGv_i64 tcg_rn = cpu_reg(s, rn); in disas_data_proc_3src()
6980 tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); in disas_data_proc_3src()
6984 tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); in disas_data_proc_3src()
6987 tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); in disas_data_proc_3src()
7018 unsigned int sf, op, setflags, rm, rn, rd; in disas_adc_sbc() local
7025 rn = extract32(insn, 5, 5); in disas_adc_sbc()
7029 tcg_rn = cpu_reg(s, rn); in disas_adc_sbc()
7056 int rn = extract32(insn, 5, 5); in disas_rotate_right_into_flags() local
7067 tcg_rn = read_cpu_reg(s, rn, 1); in disas_rotate_right_into_flags()
7098 int rn = extract32(insn, 5, 5); in disas_evaluate_into_flags() local
7113 tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); in disas_evaluate_into_flags()
7129 unsigned int sf, op, y, cond, rn, nzcv, is_imm; in disas_cc() local
7147 rn = extract32(insn, 5, 5); in disas_cc()
7162 tcg_rn = cpu_reg(s, rn); in disas_cc()
7228 unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; in disas_cond_select() local
7242 rn = extract32(insn, 5, 5); in disas_cond_select()
7250 if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { in disas_cond_select()
7260 TCGv_i64 t_true = cpu_reg(s, rn); in disas_cond_select()
7278 unsigned int rn, unsigned int rd) in handle_clz() argument
7282 tcg_rn = cpu_reg(s, rn); in handle_clz()
7295 unsigned int rn, unsigned int rd) in handle_cls() argument
7299 tcg_rn = cpu_reg(s, rn); in handle_cls()
7312 unsigned int rn, unsigned int rd) in handle_rbit() argument
7316 tcg_rn = cpu_reg(s, rn); in handle_rbit()
7330 unsigned int rn, unsigned int rd) in handle_rev64() argument
7336 tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); in handle_rev64()
7343 unsigned int rn, unsigned int rd) in handle_rev32() argument
7346 TCGv_i64 tcg_rn = cpu_reg(s, rn); in handle_rev32()
7358 unsigned int rn, unsigned int rd) in handle_rev16() argument
7362 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); in handle_rev16()
7380 unsigned int sf, opcode, opcode2, rn, rd; in disas_data_proc_1src() local
7391 rn = extract32(insn, 5, 5); in disas_data_proc_1src()
7399 handle_rbit(s, sf, rn, rd); in disas_data_proc_1src()
7403 handle_rev16(s, sf, rn, rd); in disas_data_proc_1src()
7407 handle_rev32(s, sf, rn, rd); in disas_data_proc_1src()
7410 handle_rev64(s, sf, rn, rd); in disas_data_proc_1src()
7414 handle_clz(s, sf, rn, rd); in disas_data_proc_1src()
7418 handle_cls(s, sf, rn, rd); in disas_data_proc_1src()
7423 gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7431 gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7439 gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7447 gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7455 gen_helper_autia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7463 gen_helper_autib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7471 gen_helper_autda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7479 gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); in disas_data_proc_1src()
7485 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7493 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7501 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7509 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7517 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7525 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7533 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7541 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7549 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7557 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { in disas_data_proc_1src()
7574 unsigned int rm, unsigned int rn, unsigned int rd) in handle_div() argument
7582 tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); in handle_div()
7585 tcg_n = read_cpu_reg(s, rn, sf); in handle_div()
7603 unsigned int rm, unsigned int rn, unsigned int rd) in handle_shift_reg() argument
7607 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); in handle_shift_reg()
7616 unsigned int rm, unsigned int rn, unsigned int rd) in handle_crc32() argument
7649 tcg_acc = cpu_reg(s, rn); in handle_crc32()
7667 unsigned int sf, rm, opcode, rn, rd, setflag; in disas_data_proc_2src() local
7672 rn = extract32(insn, 5, 5); in disas_data_proc_2src()
7687 tcg_n = read_cpu_reg_sp(s, rn, true); in disas_data_proc_2src()
7701 handle_div(s, false, sf, rm, rn, rd); in disas_data_proc_2src()
7704 handle_div(s, true, sf, rm, rn, rd); in disas_data_proc_2src()
7712 cpu_reg_sp(s, rn), cpu_reg(s, rm)); in disas_data_proc_2src()
7715 cpu_reg_sp(s, rn)); in disas_data_proc_2src()
7724 tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4); in disas_data_proc_2src()
7730 handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); in disas_data_proc_2src()
7733 handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); in disas_data_proc_2src()
7736 handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); in disas_data_proc_2src()
7739 handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); in disas_data_proc_2src()
7746 cpu_reg(s, rn), cpu_reg_sp(s, rm)); in disas_data_proc_2src()
7759 handle_crc32(s, sf, sz, crc32c, rm, rn, rd); in disas_data_proc_2src()
7850 unsigned int rn, unsigned int rm, in handle_fp_compare() argument
7859 tcg_vn = read_fp_dreg(s, rn); in handle_fp_compare()
7874 read_vec_element_i32(s, tcg_vn, rn, 0, size); in handle_fp_compare()
7912 unsigned int mos, type, rm, op, rn, opc, op2r; in disas_fp_compare() local
7919 rn = extract32(insn, 5, 5); in disas_fp_compare()
7950 handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); in disas_fp_compare()
7961 unsigned int mos, type, rm, cond, rn, op, nzcv; in disas_fp_ccomp() local
7969 rn = extract32(insn, 5, 5); in disas_fp_ccomp()
8010 handle_fp_compare(s, size, rn, rm, false, op); in disas_fp_ccomp()
8018 static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) in handle_fp_1src_half() argument
8021 TCGv_i32 tcg_op = read_fp_hreg(s, rn); in handle_fp_1src_half()
8068 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) in handle_fp_1src_single() argument
8075 tcg_op = read_fp_sreg(s, rn); in handle_fp_1src_single()
8140 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) in handle_fp_1src_double() argument
8149 gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); in handle_fp_1src_double()
8153 tcg_op = read_fp_dreg(s, rn); in handle_fp_1src_double()
8212 int rd, int rn, int dtype, int ntype) in handle_fp_fcvt() argument
8217 TCGv_i32 tcg_rn = read_fp_sreg(s, rn); in handle_fp_fcvt()
8237 TCGv_i64 tcg_rn = read_fp_dreg(s, rn); in handle_fp_fcvt()
8254 TCGv_i32 tcg_rn = read_fp_sreg(s, rn); in handle_fp_fcvt()
8287 int rn = extract32(insn, 5, 5); in disas_fp_1src() local
8306 handle_fp_fcvt(s, opcode, rd, rn, dtype, type); in disas_fp_1src()
8324 handle_fp_1src_single(s, opcode, rd, rn); in disas_fp_1src()
8330 handle_fp_1src_double(s, opcode, rd, rn); in disas_fp_1src()
8340 handle_fp_1src_half(s, opcode, rd, rn); in disas_fp_1src()
8356 handle_fp_1src_single(s, opcode, rd, rn); in disas_fp_1src()
8422 static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, in handle_fpfpcvt() argument
8435 TCGv_i64 tcg_int = cpu_reg(s, rn); in handle_fpfpcvt()
8503 tcg_double = read_fp_dreg(s, rn); in handle_fpfpcvt()
8527 tcg_single = read_fp_sreg(s, rn); in handle_fpfpcvt()
8550 tcg_single = read_fp_sreg(s, rn); in handle_fpfpcvt()
8589 int rn = extract32(insn, 5, 5); in disas_fp_fixed_conv() local
8635 handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); in disas_fp_fixed_conv()
8638 static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) in handle_fmov() argument
8645 TCGv_i64 tcg_rn = cpu_reg(s, rn); in handle_fmov()
8679 tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_32)); in handle_fmov()
8683 tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_64)); in handle_fmov()
8687 tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, rn)); in handle_fmov()
8691 tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_16)); in handle_fmov()
8699 static void handle_fjcvtzs(DisasContext *s, int rd, int rn) in handle_fjcvtzs() argument
8701 TCGv_i64 t = read_fp_dreg(s, rn); in handle_fjcvtzs()
8722 int rn = extract32(insn, 5, 5); in disas_fp_int_conv() local
8762 handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); in disas_fp_int_conv()
8785 handle_fmov(s, rd, rn, type, itof); in disas_fp_int_conv()
8792 handle_fjcvtzs(s, rd, rn); in disas_fp_int_conv()
8888 int rn = extract32(insn, 5, 5); in disas_simd_ext() local
8910 read_vec_element(s, tcg_resl, rn, 0, MO_64); in disas_simd_ext()
8921 EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; in disas_simd_ext()
8959 int rn = extract32(insn, 5, 5); in disas_simd_tb() local
8976 (len << 6) | (is_tbx << 5) | rn, in disas_simd_tb()
8989 int rn = extract32(insn, 5, 5); in disas_simd_zip_trn() local
9025 read_vec_element(s, tcg_ele, rn, 2 * i + part, size); in disas_simd_zip_trn()
9036 read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size); in disas_simd_zip_trn()
9045 read_vec_element(s, tcg_ele, rn, base + (i >> 1), size); in disas_simd_zip_trn()
9079 static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, in do_reduction_op() argument
9093 read_vec_element_i32(s, tcg_elem, rn, element, msize); in do_reduction_op()
9102 tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); in do_reduction_op()
9103 tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); in do_reduction_op()
9147 int rn = extract32(insn, 5, 5); in disas_simd_across_lanes() local
9220 read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); in disas_simd_across_lanes()
9223 read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); in disas_simd_across_lanes()
9258 TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, in disas_simd_across_lanes()
9437 int opcode, int rn, int rd) in handle_scalar_simd_shri() argument
9479 tcg_rn = read_fp_dreg(s, rn); in handle_scalar_simd_shri()
9502 int rn, int rd) in handle_scalar_simd_shli() argument
9519 tcg_rn = read_fp_dreg(s, rn); in handle_scalar_simd_shli()
9536 int rn, int rd) in handle_vec_simd_sqshrn() argument
9597 read_vec_element(s, tcg_rn, rn, i, ldop); in handle_vec_simd_sqshrn()
9620 int immh, int immb, int rn, int rd) in handle_simd_qshl() argument
9671 read_vec_element(s, tcg_op, rn, pass, MO_64); in handle_simd_qshl()
9700 read_vec_element_i32(s, tcg_op, rn, pass, memop); in handle_simd_qshl()
9728 static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, in handle_simd_intfp_conv() argument
9747 read_vec_element(s, tcg_int64, rn, pass, mop); in handle_simd_intfp_conv()
9767 read_vec_element_i32(s, tcg_int32, rn, pass, mop); in handle_simd_intfp_conv()
9823 int rn, int rd) in handle_simd_shift_intfp_conv() argument
9860 handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); in handle_simd_shift_intfp_conv()
9866 int immh, int immb, int rn, int rd) in handle_simd_shift_fpint_conv() argument
9911 read_vec_element(s, tcg_op, rn, pass, MO_64); in handle_simd_shift_fpint_conv()
9946 read_vec_element_i32(s, tcg_op, rn, pass, size); in handle_simd_shift_fpint_conv()
9976 int rn = extract32(insn, 5, 5); in disas_simd_scalar_shift_imm() local
9998 handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); in disas_simd_scalar_shift_imm()
10001 handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); in disas_simd_scalar_shift_imm()
10005 opcode, rn, rd); in disas_simd_scalar_shift_imm()
10014 immh, immb, opcode, rn, rd); in disas_simd_scalar_shift_imm()
10019 immh, immb, opcode, rn, rd); in disas_simd_scalar_shift_imm()
10026 handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); in disas_simd_scalar_shift_imm()
10029 handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); in disas_simd_scalar_shift_imm()
10032 handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); in disas_simd_scalar_shift_imm()
10141 int size, int rn, int rd) in handle_2misc_fcmp_zero() argument
10181 read_vec_element(s, tcg_op, rn, pass, MO_64); in handle_2misc_fcmp_zero()
10249 read_vec_element_i32(s, tcg_op, rn, pass, size); in handle_2misc_fcmp_zero()
10270 int size, int rn, int rd) in handle_2misc_reciprocal() argument
10281 read_vec_element(s, tcg_op, rn, pass, MO_64); in handle_2misc_reciprocal()
10310 read_vec_element_i32(s, tcg_op, rn, pass, MO_32); in handle_2misc_reciprocal()
10343 int size, int rn, int rd) in handle_2misc_narrow() argument
10363 read_vec_element(s, tcg_op, rn, pass, size + 1); in handle_2misc_narrow()
10365 read_vec_element(s, tcg_op, rn, pass, MO_64); in handle_2misc_narrow()
10457 int rn = extract32(insn, 5, 5); in disas_simd_scalar_two_reg_misc() local
10497 handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); in disas_simd_scalar_two_reg_misc()
10513 handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); in disas_simd_scalar_two_reg_misc()
10522 handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); in disas_simd_scalar_two_reg_misc()
10531 handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); in disas_simd_scalar_two_reg_misc()
10558 handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); in disas_simd_scalar_two_reg_misc()
10584 TCGv_i64 tcg_rn = read_fp_dreg(s, rn); in disas_simd_scalar_two_reg_misc()
10593 read_vec_element_i32(s, tcg_rn, rn, 0, size); in disas_simd_scalar_two_reg_misc()
10638 int immh, int immb, int opcode, int rn, int rd) in handle_vec_simd_shri() argument
10694 gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size); in handle_vec_simd_shri()
10699 int immh, int immb, int opcode, int rn, int rd) in handle_vec_simd_shli() argument
10718 gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size); in handle_vec_simd_shli()
10720 gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); in handle_vec_simd_shli()
10726 int immh, int immb, int opcode, int rn, int rd) in handle_vec_simd_wshli() argument
10751 read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); in handle_vec_simd_wshli()
10764 int immh, int immb, int opcode, int rn, int rd) in handle_vec_simd_shrn() argument
10798 read_vec_element(s, tcg_rn, rn, i, size+1); in handle_vec_simd_shrn()
10824 int rn = extract32(insn, 5, 5); in disas_simd_shift_imm() local
10845 handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); in disas_simd_shift_imm()
10848 handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); in disas_simd_shift_imm()
10854 opcode, rn, rd); in disas_simd_shift_imm()
10856 handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); in disas_simd_shift_imm()
10862 opcode, rn, rd); in disas_simd_shift_imm()
10865 handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); in disas_simd_shift_imm()
10869 opcode, rn, rd); in disas_simd_shift_imm()
10876 handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); in disas_simd_shift_imm()
10879 handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); in disas_simd_shift_imm()
10882 handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); in disas_simd_shift_imm()
10891 int size, int rn, int rd) in handle_2misc_widening() argument
10908 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); in handle_2misc_widening()
10924 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); in handle_2misc_widening()
10935 bool is_q, int size, int rn, int rd) in handle_rev() argument
10959 read_vec_element(s, tcg_tmp, rn, i, grp_size); in handle_rev()
10993 read_vec_element(s, tcg_rn, rn, i, size); in handle_rev()
11005 bool is_q, int size, int rn, int rd) in handle_2misc_pairwise() argument
11027 read_vec_element(s, tcg_op1, rn, pass * 2, memop); in handle_2misc_pairwise()
11028 read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); in handle_2misc_pairwise()
11048 read_vec_element(s, tcg_op, rn, pass, MO_64); in handle_2misc_pairwise()
11071 static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) in handle_shll() argument
11087 read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); in handle_shll()
11110 int rn = extract32(insn, 5, 5); in disas_simd_two_reg_misc() local
11120 handle_rev(s, opcode, u, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11145 handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11162 handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11172 handle_shll(s, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11223 handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); in disas_simd_two_reg_misc()
11235 handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11282 handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11297 handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); in disas_simd_two_reg_misc()
11307 handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); in disas_simd_two_reg_misc()
11313 handle_2misc_widening(s, opcode, is_q, size, rn, rd); in disas_simd_two_reg_misc()
11385 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); in disas_simd_two_reg_misc()
11391 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size); in disas_simd_two_reg_misc()
11393 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size); in disas_simd_two_reg_misc()
11398 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size); in disas_simd_two_reg_misc()
11400 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size); in disas_simd_two_reg_misc()
11404 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size); in disas_simd_two_reg_misc()
11408 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); in disas_simd_two_reg_misc()
11410 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); in disas_simd_two_reg_misc()
11427 read_vec_element(s, tcg_op, rn, pass, MO_64); in disas_simd_two_reg_misc()
11441 read_vec_element_i32(s, tcg_op, rn, pass, MO_32); in disas_simd_two_reg_misc()
11581 int rn, rd; in disas_simd_two_reg_misc_fp16() local
11598 rn = extract32(insn, 5, 5); in disas_simd_two_reg_misc_fp16()
11624 handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); in disas_simd_two_reg_misc_fp16()
11633 handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); in disas_simd_two_reg_misc_fp16()
11732 TCGv_i32 tcg_op = read_fp_hreg(s, rn); in disas_simd_two_reg_misc_fp16()
11774 read_vec_element_i32(s, tcg_op, rn, pass, MO_16); in disas_simd_two_reg_misc_fp16()