Lines Matching +full:low +full:- +full:profile
6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "cpu-features.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
18 #include "exec/page-protection.h"
20 #include "accel/tcg/cpu-ldst.h"
21 #include "semihosting/common-semi.h"
63 uint32_t value = env->v7m.control[secure]; in arm_v7m_mrs_control()
67 value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; in arm_v7m_mrs_control()
80 case 0 ... 7: /* xPSR sub-fields */ in HELPER()
84 /* There are no sub-fields that are actually writable from EL0. */ in HELPER()
95 case 0 ... 7: /* xPSR sub-fields */ in HELPER()
107 /* translate.c should never generate calls here in user-only mode */ in HELPER()
113 /* translate.c should never generate calls here in user-only mode */ in HELPER()
119 /* translate.c should never generate calls here in user-only mode */ in HELPER()
125 /* translate.c should never generate calls here in user-only mode */ in HELPER()
131 /* translate.c should never generate calls here in user-only mode */ in HELPER()
139 * user-only emulation we don't have the MPU. in HELPER()
188 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
197 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
216 CPUARMState *env = &cpu->env; in v7m_stack_write()
231 env->v7m.sfsr |= R_V7M_SFSR_LSPERR_MASK; in v7m_stack_write()
236 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; in v7m_stack_write()
238 env->v7m.sfsr |= R_V7M_SFSR_SFARVALID_MASK; in v7m_stack_write()
239 env->v7m.sfar = addr; in v7m_stack_write()
246 env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK; in v7m_stack_write()
250 env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; in v7m_stack_write()
263 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; in v7m_stack_write()
266 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; in v7m_stack_write()
289 armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure); in v7m_stack_write()
292 armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure); in v7m_stack_write()
304 CPUARMState *env = &cpu->env; in v7m_stack_read()
318 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; in v7m_stack_read()
319 env->v7m.sfar = addr; in v7m_stack_read()
325 env->v7m.cfsr[secure] |= R_V7M_CFSR_MUNSTKERR_MASK; in v7m_stack_read()
337 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK; in v7m_stack_read()
354 armv7m_nvic_set_pending(env->nvic, exc, exc_secure); in v7m_stack_read()
367 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER()
368 bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); in HELPER()
369 bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); in HELPER()
370 bool splimviol = env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_MASK; in HELPER()
371 uint32_t fpcar = env->v7m.fpcar[is_secure]; in HELPER()
373 bool ts = is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); in HELPER()
381 armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, is_secure); in HELPER()
382 env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; in HELPER()
384 } else if (!is_secure && !extract32(env->v7m.nsacr, 10, 1)) { in HELPER()
385 armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); in HELPER()
386 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in HELPER()
416 env->v7m.vpr, mmu_idx, STACK_LAZYFP); in HELPER()
429 armv7m_nvic_can_take_pending_exception(env->nvic); in HELPER()
437 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER()
448 env->v7m.vpr = 0; in HELPER()
469 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
470 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
474 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
479 tmp = env->v7m.other_sp; in write_v7m_control_spsel_for_secstate()
480 env->v7m.other_sp = env->regs[13]; in write_v7m_control_spsel_for_secstate()
481 env->regs[13] = tmp; in write_v7m_control_spsel_for_secstate()
492 write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure); in write_v7m_control_spsel()
504 env->v7m.exception = new_exc; in write_v7m_exception()
509 tmp = env->v7m.other_sp; in write_v7m_exception()
510 env->v7m.other_sp = env->regs[13]; in write_v7m_exception()
511 env->regs[13] = tmp; in write_v7m_exception()
515 /* Switch M profile security state between NS and S */
520 if (env->v7m.secure == new_secstate) { in switch_v7m_security_state()
525 * All the banked state is accessed by looking at env->v7m.secure in switch_v7m_security_state()
528 new_ss_msp = env->v7m.other_ss_msp; in switch_v7m_security_state()
529 new_ss_psp = env->v7m.other_ss_psp; in switch_v7m_security_state()
532 env->v7m.other_ss_psp = env->regs[13]; in switch_v7m_security_state()
533 env->v7m.other_ss_msp = env->v7m.other_sp; in switch_v7m_security_state()
535 env->v7m.other_ss_msp = env->regs[13]; in switch_v7m_security_state()
536 env->v7m.other_ss_psp = env->v7m.other_sp; in switch_v7m_security_state()
539 env->v7m.secure = new_secstate; in switch_v7m_security_state()
542 env->regs[13] = new_ss_psp; in switch_v7m_security_state()
543 env->v7m.other_sp = new_ss_msp; in switch_v7m_security_state()
545 env->regs[13] = new_ss_msp; in switch_v7m_security_state()
546 env->v7m.other_sp = new_ss_psp; in switch_v7m_security_state()
554 * - if the return value is a magic value, do exception return (like BX) in HELPER()
555 * - otherwise bit 0 of the return value is the target security state in HELPER()
572 * M profile this should count as an "instruction execution complete" in HELPER()
575 env->regs[15] = dest & ~1; in HELPER()
576 env->thumb = dest & 1; in HELPER()
582 assert(env->v7m.secure); in HELPER()
585 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in HELPER()
588 env->thumb = true; in HELPER()
589 env->regs[15] = dest & ~1; in HELPER()
597 * - bit 0 of the destination address is the target security state in HELPER()
601 uint32_t nextinst = env->regs[15] | 1; in HELPER()
602 uint32_t sp = env->regs[13] - 8; in HELPER()
606 assert(env->v7m.secure); in HELPER()
611 * except that the low bit doesn't indicate Thumb/not. in HELPER()
613 env->regs[14] = nextinst; in HELPER()
614 env->thumb = true; in HELPER()
615 env->regs[15] = dest & ~1; in HELPER()
619 /* Target is non-secure: first push a stack frame */ in HELPER()
629 saved_psr = env->v7m.exception; in HELPER()
630 if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { in HELPER()
641 env->regs[13] = sp; in HELPER()
642 env->regs[14] = 0xfeffffff; in HELPER()
646 * exception number to non-secure code. This is guaranteed not in HELPER()
651 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in HELPER()
653 env->thumb = true; in HELPER()
654 env->regs[15] = dest; in HELPER()
662 CPUARMState *env = &cpu->env; in arm_v7m_load_vector()
664 uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4; in arm_v7m_load_vector()
672 exc, targets_secure ? "secure" : "non-secure", addr); in arm_v7m_load_vector()
711 exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); in arm_v7m_load_vector()
731 if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in arm_v7m_load_vector()
734 env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK; in arm_v7m_load_vector()
736 env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; in arm_v7m_load_vector()
738 armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure); in arm_v7m_load_vector()
745 * Return the integrity signature value for the callee-saves in v7m_integrity_sig()
762 * For v8M, push the callee-saves register part of the stack frame. in v7m_push_callee_stack()
766 CPUARMState *env = &cpu->env; in v7m_push_callee_stack()
778 bool priv = !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_NPRIV_MASK) || in v7m_push_callee_stack()
786 limit = env->v7m.psplim[M_REG_S]; in v7m_push_callee_stack()
788 limit = env->v7m.msplim[M_REG_S]; in v7m_push_callee_stack()
792 frame_sp_p = &env->regs[13]; in v7m_push_callee_stack()
796 frameptr = *frame_sp_p - 0x28; in v7m_push_callee_stack()
805 "...STKOF during callee-saves register stacking\n"); in v7m_push_callee_stack()
806 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in v7m_push_callee_stack()
807 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in v7m_push_callee_stack()
808 env->v7m.secure); in v7m_push_callee_stack()
820 v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode) && in v7m_push_callee_stack()
821 v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode) && in v7m_push_callee_stack()
822 v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode) && in v7m_push_callee_stack()
823 v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode) && in v7m_push_callee_stack()
824 v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode) && in v7m_push_callee_stack()
825 v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode) && in v7m_push_callee_stack()
826 v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smode) && in v7m_push_callee_stack()
827 v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smode); in v7m_push_callee_stack()
843 CPUARMState *env = &cpu->env; in v7m_exception_taken()
849 armv7m_nvic_get_pending_irq_info(env->nvic, &exc, &targets_secure); in v7m_exception_taken()
867 * have or now needs to push callee-saves registers. in v7m_exception_taken()
873 * (which means the callee-saved registers got stacked) in v7m_exception_taken()
876 * exception unstacks the callee-saved registers. in v7m_exception_taken()
882 * We're going to a non-secure exception; push the in v7m_exception_taken()
883 * callee-saves registers to the stack now, if they're in v7m_exception_taken()
900 if (env->v7m.control[targets_secure] & R_V7M_CONTROL_SPSEL_MASK) { in v7m_exception_taken()
905 * Clear registers if necessary to prevent non-secure exception in v7m_exception_taken()
909 * here and always zeroes the caller-saved registers regardless in v7m_exception_taken()
915 * Always clear the caller-saved registers (they have been in v7m_exception_taken()
917 * Clear callee-saved registers if the background code is in v7m_exception_taken()
923 * r4..r11 are callee-saves, zero only if background in v7m_exception_taken()
925 * targets Non-secure state in v7m_exception_taken()
932 env->regs[i] = 0; in v7m_exception_taken()
943 * Derived exception on callee-saves register stacking: in v7m_exception_taken()
948 "...derived exception on callee-saves register stacking"); in v7m_exception_taken()
965 armv7m_nvic_acknowledge_irq(env->nvic); in v7m_exception_taken()
967 /* Switch to target security state -- must do this before writing SPSEL */ in v7m_exception_taken()
972 env->v7m.control[M_REG_S] &= in v7m_exception_taken()
975 env->condexec_bits = 0; in v7m_exception_taken()
976 env->regs[14] = lr; in v7m_exception_taken()
977 env->regs[15] = addr & 0xfffffffe; in v7m_exception_taken()
978 env->thumb = addr & 1; in v7m_exception_taken()
989 bool is_secure = env->v7m.secure; in v7m_update_fpccr()
990 NVICState *nvic = env->nvic; in v7m_update_fpccr()
997 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr()
998 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr()
999 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr()
1002 env->v7m.fpcar[is_secure] = frameptr & ~0x7; in v7m_update_fpccr()
1008 (env->v7m.ccr[is_secure] & R_V7M_CCR_STKOFHFNMIGN_MASK); in v7m_update_fpccr()
1051 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER()
1052 bool lspact = env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; in HELPER()
1058 assert(env->v7m.secure); in HELPER()
1060 if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { in HELPER()
1085 if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { in HELPER()
1086 bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; in HELPER()
1103 cpu_stl_mmu(env, fptr + 0x44, env->v7m.vpr, oi, ra); in HELPER()
1116 env->v7m.vpr = 0; in HELPER()
1123 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; in HELPER()
1135 assert(env->v7m.secure); in HELPER()
1137 if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { in HELPER()
1146 if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { in HELPER()
1148 env->v7m.fpccr[M_REG_S] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER()
1150 bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; in HELPER()
1176 env->v7m.vpr = cpu_ldl_mmu(env, fptr + 0x44, oi, ra); in HELPER()
1180 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; in HELPER()
1193 CPUARMState *env = &cpu->env; in v7m_push_stack()
1195 uint32_t frameptr = env->regs[13]; in v7m_push_stack()
1198 bool nsacr_cp10 = extract32(env->v7m.nsacr, 10, 1); in v7m_push_stack()
1200 if ((env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) && in v7m_push_stack()
1201 (env->v7m.secure || nsacr_cp10)) { in v7m_push_stack()
1202 if (env->v7m.secure && in v7m_push_stack()
1203 env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK) { in v7m_push_stack()
1214 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { in v7m_push_stack()
1215 frameptr -= 4; in v7m_push_stack()
1220 if (env->v7m.secure && in v7m_push_stack()
1221 (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { in v7m_push_stack()
1225 frameptr -= framesize; in v7m_push_stack()
1239 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in v7m_push_stack()
1240 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in v7m_push_stack()
1241 env->v7m.secure); in v7m_push_stack()
1242 env->regs[13] = limit; in v7m_push_stack()
1261 v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL) && in v7m_push_stack()
1262 v7m_stack_write(cpu, frameptr + 4, env->regs[1], in v7m_push_stack()
1264 v7m_stack_write(cpu, frameptr + 8, env->regs[2], in v7m_push_stack()
1266 v7m_stack_write(cpu, frameptr + 12, env->regs[3], in v7m_push_stack()
1268 v7m_stack_write(cpu, frameptr + 16, env->regs[12], in v7m_push_stack()
1270 v7m_stack_write(cpu, frameptr + 20, env->regs[14], in v7m_push_stack()
1272 v7m_stack_write(cpu, frameptr + 24, env->regs[15], in v7m_push_stack()
1276 if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { in v7m_push_stack()
1278 bool fpccr_s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in v7m_push_stack()
1279 bool lspact = env->v7m.fpccr[fpccr_s] & R_V7M_FPCCR_LSPACT_MASK; in v7m_push_stack()
1284 env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; in v7m_push_stack()
1285 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in v7m_push_stack()
1286 } else if (!env->v7m.secure && !nsacr_cp10) { in v7m_push_stack()
1290 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); in v7m_push_stack()
1291 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in v7m_push_stack()
1293 if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { in v7m_push_stack()
1296 bool cpacr_pass = v7m_cpacr_pass(env, env->v7m.secure, in v7m_push_stack()
1308 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in v7m_push_stack()
1309 env->v7m.secure); in v7m_push_stack()
1310 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; in v7m_push_stack()
1335 env->v7m.vpr, mmu_idx, STACK_NORMAL); in v7m_push_stack()
1343 env->v7m.vpr = 0; in v7m_push_stack()
1359 env->regs[13] = frameptr; in v7m_push_stack()
1367 CPUARMState *env = &cpu->env; in do_v7m_exception_exit()
1381 * If we're not in Handler mode then jumps to magic exception-exit in do_v7m_exception_exit()
1383 * security extensions the magic secure-function-return has to in do_v7m_exception_exit()
1385 * the generated code we allow exception-exit magic to also cause the in do_v7m_exception_exit()
1399 * jump-to-register (which is then caught later on), and so split in do_v7m_exception_exit()
1400 * the target value up between env->regs[15] and env->thumb in in do_v7m_exception_exit()
1403 excret = env->regs[15]; in do_v7m_exception_exit()
1404 if (env->thumb) { in do_v7m_exception_exit()
1410 excret, env->v7m.exception); in do_v7m_exception_exit()
1413 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " in do_v7m_exception_exit()
1421 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " in do_v7m_exception_exit()
1433 if (!env->v7m.secure && in do_v7m_exception_exit()
1443 if (env->v7m.exception != ARMV7M_EXCP_NMI) { in do_v7m_exception_exit()
1445 * Auto-clear FAULTMASK on return from other than NMI. in do_v7m_exception_exit()
1452 if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { in do_v7m_exception_exit()
1453 env->v7m.faultmask[exc_secure] = 0; in do_v7m_exception_exit()
1456 env->v7m.faultmask[M_REG_NS] = 0; in do_v7m_exception_exit()
1460 switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception, in do_v7m_exception_exit()
1462 case -1: in do_v7m_exception_exit()
1502 /* For v7M we only recognize certain combinations of the low bits */ in do_v7m_exception_exit()
1513 !(env->v7m.ccr[env->v7m.secure] & in do_v7m_exception_exit()
1537 if ((env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_CLRONRET_MASK) && in do_v7m_exception_exit()
1538 (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { in do_v7m_exception_exit()
1539 if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { in do_v7m_exception_exit()
1540 env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; in do_v7m_exception_exit()
1541 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in do_v7m_exception_exit()
1550 extract32(env->v7m.nsacr, 10, 1); in do_v7m_exception_exit()
1553 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true); in do_v7m_exception_exit()
1554 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in do_v7m_exception_exit()
1560 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in do_v7m_exception_exit()
1562 env->v7m.cfsr[exc_secure] |= R_V7M_CFSR_NOCP_MASK; in do_v7m_exception_exit()
1577 env->v7m.vpr = 0; in do_v7m_exception_exit()
1583 env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK; in do_v7m_exception_exit()
1584 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in do_v7m_exception_exit()
1596 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; in do_v7m_exception_exit()
1597 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); in do_v7m_exception_exit()
1608 * avoiding an unstack-and-then-stack. Note that now we have in do_v7m_exception_exit()
1611 * returning to -- none of the state we would unstack or set based on in do_v7m_exception_exit()
1614 if (armv7m_nvic_can_take_pending_exception(env->nvic)) { in do_v7m_exception_exit()
1633 bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; in do_v7m_exception_exit()
1640 !(env->v7m.control[return_to_secure] & R_V7M_CONTROL_NPRIV_MASK); in do_v7m_exception_exit()
1648 "M profile exception return with non-8-aligned SP " in do_v7m_exception_exit()
1652 /* Do we need to pop callee-saved registers? */ in do_v7m_exception_exit()
1662 env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK; in do_v7m_exception_exit()
1663 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in do_v7m_exception_exit()
1672 v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) && in do_v7m_exception_exit()
1673 v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx) && in do_v7m_exception_exit()
1674 v7m_stack_read(cpu, &env->regs[6], frameptr + 0x10, mmu_idx) && in do_v7m_exception_exit()
1675 v7m_stack_read(cpu, &env->regs[7], frameptr + 0x14, mmu_idx) && in do_v7m_exception_exit()
1676 v7m_stack_read(cpu, &env->regs[8], frameptr + 0x18, mmu_idx) && in do_v7m_exception_exit()
1677 v7m_stack_read(cpu, &env->regs[9], frameptr + 0x1c, mmu_idx) && in do_v7m_exception_exit()
1678 v7m_stack_read(cpu, &env->regs[10], frameptr + 0x20, mmu_idx) && in do_v7m_exception_exit()
1679 v7m_stack_read(cpu, &env->regs[11], frameptr + 0x24, mmu_idx); in do_v7m_exception_exit()
1686 v7m_stack_read(cpu, &env->regs[0], frameptr, mmu_idx) && in do_v7m_exception_exit()
1687 v7m_stack_read(cpu, &env->regs[1], frameptr + 0x4, mmu_idx) && in do_v7m_exception_exit()
1688 v7m_stack_read(cpu, &env->regs[2], frameptr + 0x8, mmu_idx) && in do_v7m_exception_exit()
1689 v7m_stack_read(cpu, &env->regs[3], frameptr + 0xc, mmu_idx) && in do_v7m_exception_exit()
1690 v7m_stack_read(cpu, &env->regs[12], frameptr + 0x10, mmu_idx) && in do_v7m_exception_exit()
1691 v7m_stack_read(cpu, &env->regs[14], frameptr + 0x14, mmu_idx) && in do_v7m_exception_exit()
1692 v7m_stack_read(cpu, &env->regs[15], frameptr + 0x18, mmu_idx) && in do_v7m_exception_exit()
1710 * assume the r15 in the stack frame should be a Thumb-style "lsbit in do_v7m_exception_exit()
1714 if (env->regs[15] & 1) { in do_v7m_exception_exit()
1715 env->regs[15] &= ~1U; in do_v7m_exception_exit()
1718 "M profile return from interrupt with misaligned " in do_v7m_exception_exit()
1737 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in do_v7m_exception_exit()
1738 env->v7m.secure); in do_v7m_exception_exit()
1739 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; in do_v7m_exception_exit()
1751 (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK)) { in do_v7m_exception_exit()
1752 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in do_v7m_exception_exit()
1753 env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; in do_v7m_exception_exit()
1763 (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); in do_v7m_exception_exit()
1765 if (env->v7m.fpccr[return_to_secure] & R_V7M_FPCCR_LSPACT_MASK) { in do_v7m_exception_exit()
1767 env->v7m.fpccr[return_to_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in do_v7m_exception_exit()
1776 extract32(env->v7m.nsacr, 10, 1); in do_v7m_exception_exit()
1779 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in do_v7m_exception_exit()
1781 env->v7m.cfsr[return_to_secure] |= R_V7M_CFSR_NOCP_MASK; in do_v7m_exception_exit()
1789 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true); in do_v7m_exception_exit()
1790 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_INVPC_MASK; in do_v7m_exception_exit()
1826 v7m_stack_read(cpu, &env->v7m.vpr, in do_v7m_exception_exit()
1839 env->v7m.vpr = 0; in do_v7m_exception_exit()
1844 env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], in do_v7m_exception_exit()
1857 * pre-exception SP was not 8-aligned and we added a padding word to in do_v7m_exception_exit()
1859 * from the current 8-aligned value to the 8-unaligned value. (Adding 4 in do_v7m_exception_exit()
1875 if (env->v7m.secure) { in do_v7m_exception_exit()
1878 env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], in do_v7m_exception_exit()
1896 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); in do_v7m_exception_exit()
1897 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; in do_v7m_exception_exit()
1921 * At this point the magic return value is split between env->regs[15] in do_v7m_function_return()
1922 * and env->thumb. We don't bother to reconstitute it because we don't in do_v7m_function_return()
1925 CPUARMState *env = &cpu->env; in do_v7m_function_return()
1939 spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; in do_v7m_function_return()
1955 if (!((env->v7m.exception == 0 && newpsr_exc == 0) || in do_v7m_function_return()
1956 (env->v7m.exception == 1 && newpsr_exc != 0))) { in do_v7m_function_return()
1958 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; in do_v7m_function_return()
1959 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in do_v7m_function_return()
1960 env->v7m.secure); in do_v7m_function_return()
1972 env->v7m.exception = newpsr_exc; in do_v7m_function_return()
1973 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in do_v7m_function_return()
1975 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK; in do_v7m_function_return()
1978 env->thumb = newpc & 1; in do_v7m_function_return()
1979 env->regs[15] = newpc & ~1; in do_v7m_function_return()
1990 * Load a 16-bit portion of a v7M instruction, returning true on success, in v7m_read_half_insn()
2002 CPUARMState *env = &cpu->env; in v7m_read_half_insn()
2014 env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; in v7m_read_half_insn()
2015 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in v7m_read_half_insn()
2022 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; in v7m_read_half_insn()
2023 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); in v7m_read_half_insn()
2030 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; in v7m_read_half_insn()
2031 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); in v7m_read_half_insn()
2050 CPUARMState *env = &cpu->env; in v7m_read_sg_stack_word()
2061 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; in v7m_read_sg_stack_word()
2062 env->v7m.sfar = addr; in v7m_read_sg_stack_word()
2063 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in v7m_read_sg_stack_word()
2067 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_DACCVIOL_MASK | in v7m_read_sg_stack_word()
2069 env->v7m.mmfar[M_REG_S] = addr; in v7m_read_sg_stack_word()
2070 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false); in v7m_read_sg_stack_word()
2080 env->v7m.cfsr[M_REG_NS] |= in v7m_read_sg_stack_word()
2082 env->v7m.bfar = addr; in v7m_read_sg_stack_word()
2083 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); in v7m_read_sg_stack_word()
2094 * Check whether this attempt to execute code in a Secure & NS-Callable in v7m_handle_execute_nsc()
2099 CPUARMState *env = &cpu->env; in v7m_handle_execute_nsc()
2107 assert(!env->v7m.secure); in v7m_handle_execute_nsc()
2113 if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) { in v7m_handle_execute_nsc()
2117 if (!env->thumb) { in v7m_handle_execute_nsc()
2124 * early-SG-check option). in v7m_handle_execute_nsc()
2129 if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) { in v7m_handle_execute_nsc()
2146 ", executing it\n", env->regs[15]); in v7m_handle_execute_nsc()
2161 sp = v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other_ss_msp; in v7m_handle_execute_nsc()
2167 if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { in v7m_handle_execute_nsc()
2169 !(env->v7m.control[M_REG_S] & 1)) { in v7m_handle_execute_nsc()
2175 env->regs[14] &= ~1; in v7m_handle_execute_nsc()
2176 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in v7m_handle_execute_nsc()
2179 env->regs[15] += 4; in v7m_handle_execute_nsc()
2184 env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; in v7m_handle_execute_nsc()
2185 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in v7m_handle_execute_nsc()
2194 CPUARMState *env = &cpu->env; in arm_v7m_cpu_do_interrupt()
2204 switch (cs->exception_index) { in arm_v7m_cpu_do_interrupt()
2206 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2207 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; in arm_v7m_cpu_do_interrupt()
2218 if (env->exception.target_el == 3) { in arm_v7m_cpu_do_interrupt()
2221 target_secstate = env->v7m.secure; in arm_v7m_cpu_do_interrupt()
2223 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secstate); in arm_v7m_cpu_do_interrupt()
2224 env->v7m.cfsr[target_secstate] |= R_V7M_CFSR_NOCP_MASK; in arm_v7m_cpu_do_interrupt()
2228 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2229 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; in arm_v7m_cpu_do_interrupt()
2232 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2233 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in arm_v7m_cpu_do_interrupt()
2236 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in arm_v7m_cpu_do_interrupt()
2237 env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; in arm_v7m_cpu_do_interrupt()
2240 /* Unaligned faults reported by M-profile aware code */ in arm_v7m_cpu_do_interrupt()
2241 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2242 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; in arm_v7m_cpu_do_interrupt()
2245 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2246 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_DIVBYZERO_MASK; in arm_v7m_cpu_do_interrupt()
2250 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2255 * Note that for M profile we don't have a guest facing FSR, but in arm_v7m_cpu_do_interrupt()
2256 * the env->exception.fsr will be populated by the code that in arm_v7m_cpu_do_interrupt()
2257 * raises the fault, in the A profile short-descriptor format. in arm_v7m_cpu_do_interrupt()
2264 (uint32_t)env->exception.vaddress); in arm_v7m_cpu_do_interrupt()
2265 switch (env->exception.fsr & 0xf) { in arm_v7m_cpu_do_interrupt()
2269 * which is marked as Secure & Non-Secure Callable and the CPU in arm_v7m_cpu_do_interrupt()
2270 * is in the Non-Secure state. The only instruction which can in arm_v7m_cpu_do_interrupt()
2285 switch (cs->exception_index) { in arm_v7m_cpu_do_interrupt()
2287 if (env->v7m.secure) { in arm_v7m_cpu_do_interrupt()
2288 env->v7m.sfsr |= R_V7M_SFSR_INVTRAN_MASK; in arm_v7m_cpu_do_interrupt()
2292 env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; in arm_v7m_cpu_do_interrupt()
2299 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; in arm_v7m_cpu_do_interrupt()
2304 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); in arm_v7m_cpu_do_interrupt()
2307 switch (cs->exception_index) { in arm_v7m_cpu_do_interrupt()
2309 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; in arm_v7m_cpu_do_interrupt()
2313 env->v7m.cfsr[M_REG_NS] |= in arm_v7m_cpu_do_interrupt()
2315 env->v7m.bfar = env->exception.vaddress; in arm_v7m_cpu_do_interrupt()
2318 env->v7m.bfar); in arm_v7m_cpu_do_interrupt()
2321 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); in arm_v7m_cpu_do_interrupt()
2326 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; in arm_v7m_cpu_do_interrupt()
2327 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, in arm_v7m_cpu_do_interrupt()
2328 env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2333 * for M profile" cases. in arm_v7m_cpu_do_interrupt()
2335 switch (cs->exception_index) { in arm_v7m_cpu_do_interrupt()
2337 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; in arm_v7m_cpu_do_interrupt()
2341 env->v7m.cfsr[env->v7m.secure] |= in arm_v7m_cpu_do_interrupt()
2343 env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; in arm_v7m_cpu_do_interrupt()
2346 env->v7m.mmfar[env->v7m.secure]); in arm_v7m_cpu_do_interrupt()
2349 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, in arm_v7m_cpu_do_interrupt()
2350 env->v7m.secure); in arm_v7m_cpu_do_interrupt()
2357 env->regs[0]); in arm_v7m_cpu_do_interrupt()
2363 env->regs[15] += env->thumb ? 2 : 4; in arm_v7m_cpu_do_interrupt()
2366 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); in arm_v7m_cpu_do_interrupt()
2371 if (env->regs[15] < EXC_RETURN_MIN_MAGIC) { in arm_v7m_cpu_do_interrupt()
2373 assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC); in arm_v7m_cpu_do_interrupt()
2390 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_v7m_cpu_do_interrupt()
2409 if (env->v7m.secure) { in arm_v7m_cpu_do_interrupt()
2417 if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { in arm_v7m_cpu_do_interrupt()
2421 if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { in arm_v7m_cpu_do_interrupt()
2438 case 0 ... 7: /* xPSR sub-fields */ in HELPER()
2441 return arm_v7m_mrs_control(env, env->v7m.secure); in HELPER()
2447 if (!env->v7m.secure) { in HELPER()
2450 return env->v7m.control[M_REG_NS] | in HELPER()
2451 (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK); in HELPER()
2461 if (!env->v7m.secure) { in HELPER()
2464 return env->v7m.other_ss_msp; in HELPER()
2466 if (!env->v7m.secure) { in HELPER()
2469 return env->v7m.other_ss_psp; in HELPER()
2471 if (!env->v7m.secure) { in HELPER()
2474 return env->v7m.msplim[M_REG_NS]; in HELPER()
2476 if (!env->v7m.secure) { in HELPER()
2479 return env->v7m.psplim[M_REG_NS]; in HELPER()
2481 if (!env->v7m.secure) { in HELPER()
2484 return env->v7m.primask[M_REG_NS]; in HELPER()
2489 if (!env->v7m.secure) { in HELPER()
2492 return env->v7m.basepri[M_REG_NS]; in HELPER()
2497 if (!env->v7m.secure) { in HELPER()
2500 return env->v7m.faultmask[M_REG_NS]; in HELPER()
2504 * This gives the non-secure SP selected based on whether we're in HELPER()
2507 bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; in HELPER()
2509 if (!env->v7m.secure) { in HELPER()
2513 return env->v7m.other_ss_psp; in HELPER()
2515 return env->v7m.other_ss_msp; in HELPER()
2525 return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; in HELPER()
2527 return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; in HELPER()
2532 return env->v7m.msplim[env->v7m.secure]; in HELPER()
2537 return env->v7m.psplim[env->v7m.secure]; in HELPER()
2539 return env->v7m.primask[env->v7m.secure]; in HELPER()
2545 return env->v7m.basepri[env->v7m.secure]; in HELPER()
2550 return env->v7m.faultmask[env->v7m.secure]; in HELPER()
2575 * only xPSR sub-fields and CONTROL.SFPA may be written by in HELPER()
2584 if (!env->v7m.secure) { in HELPER()
2587 env->v7m.other_ss_msp = val & ~3; in HELPER()
2590 if (!env->v7m.secure) { in HELPER()
2593 env->v7m.other_ss_psp = val & ~3; in HELPER()
2596 if (!env->v7m.secure) { in HELPER()
2599 env->v7m.msplim[M_REG_NS] = val & ~7; in HELPER()
2602 if (!env->v7m.secure) { in HELPER()
2605 env->v7m.psplim[M_REG_NS] = val & ~7; in HELPER()
2608 if (!env->v7m.secure) { in HELPER()
2611 env->v7m.primask[M_REG_NS] = val & 1; in HELPER()
2617 if (!env->v7m.secure) { in HELPER()
2620 env->v7m.basepri[M_REG_NS] = val & 0xff; in HELPER()
2626 if (!env->v7m.secure) { in HELPER()
2629 env->v7m.faultmask[M_REG_NS] = val & 1; in HELPER()
2632 if (!env->v7m.secure) { in HELPER()
2639 env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; in HELPER()
2640 env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; in HELPER()
2647 extract32(env->v7m.nsacr, 10, 1)) { in HELPER()
2648 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; in HELPER()
2649 env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; in HELPER()
2655 * This gives the non-secure SP selected based on whether we're in HELPER()
2658 bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; in HELPER()
2662 if (!env->v7m.secure) { in HELPER()
2666 limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false]; in HELPER()
2675 env->v7m.other_ss_psp = val; in HELPER()
2677 env->v7m.other_ss_msp = val; in HELPER()
2687 case 0 ... 7: /* xPSR sub-fields */ in HELPER()
2692 env->v7m.other_sp = val & ~3; in HELPER()
2694 env->regs[13] = val & ~3; in HELPER()
2699 env->regs[13] = val & ~3; in HELPER()
2701 env->v7m.other_sp = val & ~3; in HELPER()
2708 env->v7m.msplim[env->v7m.secure] = val & ~7; in HELPER()
2714 env->v7m.psplim[env->v7m.secure] = val & ~7; in HELPER()
2717 env->v7m.primask[env->v7m.secure] = val & 1; in HELPER()
2723 env->v7m.basepri[env->v7m.secure] = val & 0xff; in HELPER()
2730 if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] in HELPER()
2731 || env->v7m.basepri[env->v7m.secure] == 0)) { in HELPER()
2732 env->v7m.basepri[env->v7m.secure] = val; in HELPER()
2739 env->v7m.faultmask[env->v7m.secure] = val & 1; in HELPER()
2746 * env->v7m.control, so we only need update the others. in HELPER()
2749 * All these bits are writes-ignored from non-privileged code, in HELPER()
2757 env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; in HELPER()
2758 env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; in HELPER()
2766 if (env->v7m.secure) { in HELPER()
2767 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in HELPER()
2768 env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_SFPA_MASK; in HELPER()
2771 (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURITY) || in HELPER()
2772 extract32(env->v7m.nsacr, 10, 1))) { in HELPER()
2773 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; in HELPER()
2774 env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; in HELPER()
2797 bool targetsec = env->v7m.secure; in HELPER()
2811 !(env->v7m.control[targetsec] & R_V7M_CONTROL_NPRIV_MASK); in HELPER()
2834 if (mregion == -1) { in HELPER()
2849 if (env->v7m.secure) { in HELPER()
2889 * function in handling of pushing of the callee-saves registers in arm_v7m_get_sp_ptr()
2893 * opencodes the stack-selection in PushCalleeStack(), but we prefer in arm_v7m_get_sp_ptr()
2898 if (secure == env->v7m.secure) { in arm_v7m_get_sp_ptr()
2900 return &env->regs[13]; in arm_v7m_get_sp_ptr()
2902 return &env->v7m.other_sp; in arm_v7m_get_sp_ptr()
2906 return &env->v7m.other_ss_psp; in arm_v7m_get_sp_ptr()
2908 return &env->v7m.other_ss_msp; in arm_v7m_get_sp_ptr()