Lines Matching +full:1 +full:v8
24 # VLLDM and VLSTM. (Compare v8.1M IsCPInstruction() pseudocode and
25 # v8M Arm ARM rule R_QLGM.) This isn't mandatory for v8.0M but we choose
26 # to behave the same as v8.1M.
32 %vd_dp 22:1 12:4
33 %vd_sp 12:4 22:1
38 %vldr_sysreg 22:1 13:3
42 @vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
47 VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000
48 # VSCCLRM (new in v8.1M) is similar:
60 VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
63 VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
64 VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
65 VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1
66 VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
70 # From v8.1M onwards this range will also NOCP: