Lines Matching +full:0 +full:x00000043
48 cpu->midr = 0x411fd040; in aarch64_a35_initfn()
49 cpu->revidr = 0; in aarch64_a35_initfn()
50 cpu->ctr = 0x84448004; in aarch64_a35_initfn()
51 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a35_initfn()
52 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a35_initfn()
53 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a35_initfn()
54 cpu->id_afr0 = 0; in aarch64_a35_initfn()
55 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a35_initfn()
56 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a35_initfn()
57 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a35_initfn()
58 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a35_initfn()
59 cpu->isar.id_isar0 = 0x02101110; in aarch64_a35_initfn()
60 cpu->isar.id_isar1 = 0x13112111; in aarch64_a35_initfn()
61 cpu->isar.id_isar2 = 0x21232042; in aarch64_a35_initfn()
62 cpu->isar.id_isar3 = 0x01112131; in aarch64_a35_initfn()
63 cpu->isar.id_isar4 = 0x00011142; in aarch64_a35_initfn()
64 cpu->isar.id_isar5 = 0x00011121; in aarch64_a35_initfn()
65 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a35_initfn()
66 cpu->isar.id_aa64pfr1 = 0; in aarch64_a35_initfn()
67 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a35_initfn()
68 cpu->isar.id_aa64dfr1 = 0; in aarch64_a35_initfn()
69 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a35_initfn()
70 cpu->isar.id_aa64isar1 = 0; in aarch64_a35_initfn()
71 cpu->isar.id_aa64mmfr0 = 0x00101122; in aarch64_a35_initfn()
72 cpu->isar.id_aa64mmfr1 = 0; in aarch64_a35_initfn()
73 cpu->clidr = 0x0a200023; in aarch64_a35_initfn()
77 cpu->reset_sctlr = 0x00c50838; in aarch64_a35_initfn()
80 cpu->isar.reset_pmcr_el0 = 0x410a3000; in aarch64_a35_initfn()
84 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a35_initfn()
97 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a35_initfn()
99 cpu->isar.dbgdevid = 0x00110f13; in aarch64_a35_initfn()
101 cpu->isar.dbgdevid1 = 0x2; in aarch64_a35_initfn()
105 cpu->reset_fpsid = 0x41034043; in aarch64_a35_initfn()
108 cpu->isar.mvfr0 = 0x10110222; in aarch64_a35_initfn()
109 cpu->isar.mvfr1 = 0x12111111; in aarch64_a35_initfn()
110 cpu->isar.mvfr2 = 0x00000043; in aarch64_a35_initfn()
124 value = 0; in cpu_max_get_sve_max_vq()
141 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { in cpu_max_set_sve_max_vq()
220 cpu->clidr = 0x82000023; in aarch64_a55_initfn()
221 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ in aarch64_a55_initfn()
223 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; in aarch64_a55_initfn()
224 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_a55_initfn()
225 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_a55_initfn()
226 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; in aarch64_a55_initfn()
227 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a55_initfn()
228 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_a55_initfn()
229 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; in aarch64_a55_initfn()
230 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; in aarch64_a55_initfn()
231 cpu->id_afr0 = 0x00000000; in aarch64_a55_initfn()
232 cpu->isar.id_dfr0 = 0x04010088; in aarch64_a55_initfn()
233 cpu->isar.id_isar0 = 0x02101110; in aarch64_a55_initfn()
234 cpu->isar.id_isar1 = 0x13112111; in aarch64_a55_initfn()
235 cpu->isar.id_isar2 = 0x21232042; in aarch64_a55_initfn()
236 cpu->isar.id_isar3 = 0x01112131; in aarch64_a55_initfn()
237 cpu->isar.id_isar4 = 0x00011142; in aarch64_a55_initfn()
238 cpu->isar.id_isar5 = 0x01011121; in aarch64_a55_initfn()
239 cpu->isar.id_isar6 = 0x00000010; in aarch64_a55_initfn()
240 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a55_initfn()
241 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a55_initfn()
242 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a55_initfn()
243 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a55_initfn()
244 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_a55_initfn()
245 cpu->isar.id_pfr0 = 0x10010131; in aarch64_a55_initfn()
246 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a55_initfn()
247 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a55_initfn()
248 cpu->midr = 0x412FD050; /* r2p0 */ in aarch64_a55_initfn()
249 cpu->revidr = 0; in aarch64_a55_initfn()
253 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a55_initfn()
260 cpu->reset_sctlr = 0x30c50838; in aarch64_a55_initfn()
268 cpu->isar.mvfr0 = 0x10110222; in aarch64_a55_initfn()
269 cpu->isar.mvfr1 = 0x13211111; in aarch64_a55_initfn()
270 cpu->isar.mvfr2 = 0x00000043; in aarch64_a55_initfn()
273 cpu->isar.reset_pmcr_el0 = 0x410b3000; in aarch64_a55_initfn()
290 cpu->midr = 0x410fd083; in aarch64_a72_initfn()
291 cpu->revidr = 0x00000000; in aarch64_a72_initfn()
292 cpu->reset_fpsid = 0x41034080; in aarch64_a72_initfn()
293 cpu->isar.mvfr0 = 0x10110222; in aarch64_a72_initfn()
294 cpu->isar.mvfr1 = 0x12111111; in aarch64_a72_initfn()
295 cpu->isar.mvfr2 = 0x00000043; in aarch64_a72_initfn()
296 cpu->ctr = 0x8444c004; in aarch64_a72_initfn()
297 cpu->reset_sctlr = 0x00c50838; in aarch64_a72_initfn()
298 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a72_initfn()
299 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a72_initfn()
300 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a72_initfn()
301 cpu->id_afr0 = 0x00000000; in aarch64_a72_initfn()
302 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a72_initfn()
303 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a72_initfn()
304 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a72_initfn()
305 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a72_initfn()
306 cpu->isar.id_isar0 = 0x02101110; in aarch64_a72_initfn()
307 cpu->isar.id_isar1 = 0x13112111; in aarch64_a72_initfn()
308 cpu->isar.id_isar2 = 0x21232042; in aarch64_a72_initfn()
309 cpu->isar.id_isar3 = 0x01112131; in aarch64_a72_initfn()
310 cpu->isar.id_isar4 = 0x00011142; in aarch64_a72_initfn()
311 cpu->isar.id_isar5 = 0x00011121; in aarch64_a72_initfn()
312 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a72_initfn()
313 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a72_initfn()
314 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a72_initfn()
315 cpu->isar.id_aa64mmfr0 = 0x00001124; in aarch64_a72_initfn()
316 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a72_initfn()
317 cpu->isar.dbgdevid = 0x01110f13; in aarch64_a72_initfn()
318 cpu->isar.dbgdevid1 = 0x2; in aarch64_a72_initfn()
319 cpu->isar.reset_pmcr_el0 = 0x41023000; in aarch64_a72_initfn()
320 cpu->clidr = 0x0a200023; in aarch64_a72_initfn()
322 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a72_initfn()
351 cpu->clidr = 0x82000023; in aarch64_a76_initfn()
352 cpu->ctr = 0x8444C004; in aarch64_a76_initfn()
354 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; in aarch64_a76_initfn()
355 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_a76_initfn()
356 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_a76_initfn()
357 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; in aarch64_a76_initfn()
358 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a76_initfn()
359 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_a76_initfn()
360 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ in aarch64_a76_initfn()
361 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; in aarch64_a76_initfn()
362 cpu->id_afr0 = 0x00000000; in aarch64_a76_initfn()
363 cpu->isar.id_dfr0 = 0x04010088; in aarch64_a76_initfn()
364 cpu->isar.id_isar0 = 0x02101110; in aarch64_a76_initfn()
365 cpu->isar.id_isar1 = 0x13112111; in aarch64_a76_initfn()
366 cpu->isar.id_isar2 = 0x21232042; in aarch64_a76_initfn()
367 cpu->isar.id_isar3 = 0x01112131; in aarch64_a76_initfn()
368 cpu->isar.id_isar4 = 0x00010142; in aarch64_a76_initfn()
369 cpu->isar.id_isar5 = 0x01011121; in aarch64_a76_initfn()
370 cpu->isar.id_isar6 = 0x00000010; in aarch64_a76_initfn()
371 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a76_initfn()
372 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a76_initfn()
373 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a76_initfn()
374 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a76_initfn()
375 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_a76_initfn()
376 cpu->isar.id_pfr0 = 0x10010131; in aarch64_a76_initfn()
377 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_a76_initfn()
378 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a76_initfn()
379 cpu->midr = 0x414fd0b1; /* r4p1 */ in aarch64_a76_initfn()
380 cpu->revidr = 0; in aarch64_a76_initfn()
384 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); in aarch64_a76_initfn()
391 cpu->reset_sctlr = 0x30c50838; in aarch64_a76_initfn()
400 cpu->isar.mvfr0 = 0x10110222; in aarch64_a76_initfn()
401 cpu->isar.mvfr1 = 0x13211111; in aarch64_a76_initfn()
402 cpu->isar.mvfr2 = 0x00000043; in aarch64_a76_initfn()
405 cpu->isar.reset_pmcr_el0 = 0x410b3000; in aarch64_a76_initfn()
421 cpu->midr = 0x461f0010; in aarch64_a64fx_initfn()
422 cpu->revidr = 0x00000000; in aarch64_a64fx_initfn()
423 cpu->ctr = 0x86668006; in aarch64_a64fx_initfn()
424 cpu->reset_sctlr = 0x30000180; in aarch64_a64fx_initfn()
425 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ in aarch64_a64fx_initfn()
426 cpu->isar.id_aa64pfr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
427 cpu->isar.id_aa64dfr0 = 0x0000000010305408; in aarch64_a64fx_initfn()
428 cpu->isar.id_aa64dfr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
429 cpu->id_aa64afr0 = 0x0000000000000000; in aarch64_a64fx_initfn()
430 cpu->id_aa64afr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
431 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; in aarch64_a64fx_initfn()
432 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; in aarch64_a64fx_initfn()
433 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; in aarch64_a64fx_initfn()
434 cpu->isar.id_aa64isar0 = 0x0000000010211120; in aarch64_a64fx_initfn()
435 cpu->isar.id_aa64isar1 = 0x0000000000010001; in aarch64_a64fx_initfn()
436 cpu->isar.id_aa64zfr0 = 0x0000000000000000; in aarch64_a64fx_initfn()
437 cpu->clidr = 0x0000000080000023; in aarch64_a64fx_initfn()
439 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7); in aarch64_a64fx_initfn()
452 cpu->sve_vq.supported = (1 << 0) /* 128bit */ in aarch64_a64fx_initfn()
456 cpu->isar.reset_pmcr_el0 = 0x46014040; in aarch64_a64fx_initfn()
467 /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ in access_actlr_w()
471 /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ in access_actlr_w()
481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
487 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
490 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
493 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
496 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
507 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
522 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
525 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
528 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
530 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
531 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
533 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
534 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
537 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
538 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
541 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
542 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
545 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
546 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
557 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
558 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
561 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
562 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
565 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
568 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
597 cpu->clidr = 0x82000023; in aarch64_neoverse_n1_initfn()
598 cpu->ctr = 0x8444c004; in aarch64_neoverse_n1_initfn()
600 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; in aarch64_neoverse_n1_initfn()
601 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_neoverse_n1_initfn()
602 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_neoverse_n1_initfn()
603 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; in aarch64_neoverse_n1_initfn()
604 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_n1_initfn()
605 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_neoverse_n1_initfn()
606 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ in aarch64_neoverse_n1_initfn()
607 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; in aarch64_neoverse_n1_initfn()
608 cpu->id_afr0 = 0x00000000; in aarch64_neoverse_n1_initfn()
609 cpu->isar.id_dfr0 = 0x04010088; in aarch64_neoverse_n1_initfn()
610 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_n1_initfn()
611 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_n1_initfn()
612 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_n1_initfn()
613 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_n1_initfn()
614 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_n1_initfn()
615 cpu->isar.id_isar5 = 0x01011121; in aarch64_neoverse_n1_initfn()
616 cpu->isar.id_isar6 = 0x00000010; in aarch64_neoverse_n1_initfn()
617 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_n1_initfn()
618 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_n1_initfn()
619 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_n1_initfn()
620 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_n1_initfn()
621 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_neoverse_n1_initfn()
622 cpu->isar.id_pfr0 = 0x10010131; in aarch64_neoverse_n1_initfn()
623 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_n1_initfn()
624 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_n1_initfn()
625 cpu->midr = 0x414fd0c1; /* r4p1 */ in aarch64_neoverse_n1_initfn()
626 cpu->revidr = 0; in aarch64_neoverse_n1_initfn()
630 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); in aarch64_neoverse_n1_initfn()
637 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_n1_initfn()
646 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_n1_initfn()
647 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_n1_initfn()
648 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_n1_initfn()
651 cpu->isar.reset_pmcr_el0 = 0x410c3000; in aarch64_neoverse_n1_initfn()
672 cpu->clidr = 0x82000023; in aarch64_neoverse_v1_initfn()
673 cpu->ctr = 0xb444c004; /* With DIC and IDC set */ in aarch64_neoverse_v1_initfn()
675 cpu->id_aa64afr0 = 0x00000000; in aarch64_neoverse_v1_initfn()
676 cpu->id_aa64afr1 = 0x00000000; in aarch64_neoverse_v1_initfn()
677 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; in aarch64_neoverse_v1_initfn()
678 cpu->isar.id_aa64dfr1 = 0x00000000; in aarch64_neoverse_v1_initfn()
679 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ in aarch64_neoverse_v1_initfn()
680 cpu->isar.id_aa64isar1 = 0x0011100001211032ull; in aarch64_neoverse_v1_initfn()
681 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; in aarch64_neoverse_v1_initfn()
682 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_v1_initfn()
683 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull; in aarch64_neoverse_v1_initfn()
684 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ in aarch64_neoverse_v1_initfn()
685 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; in aarch64_neoverse_v1_initfn()
686 cpu->id_afr0 = 0x00000000; in aarch64_neoverse_v1_initfn()
687 cpu->isar.id_dfr0 = 0x15011099; in aarch64_neoverse_v1_initfn()
688 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_v1_initfn()
689 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_v1_initfn()
690 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_v1_initfn()
691 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_v1_initfn()
692 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_v1_initfn()
693 cpu->isar.id_isar5 = 0x11011121; in aarch64_neoverse_v1_initfn()
694 cpu->isar.id_isar6 = 0x01100111; in aarch64_neoverse_v1_initfn()
695 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_v1_initfn()
696 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_v1_initfn()
697 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_v1_initfn()
698 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_v1_initfn()
699 cpu->isar.id_mmfr4 = 0x01021110; in aarch64_neoverse_v1_initfn()
700 cpu->isar.id_pfr0 = 0x21110131; in aarch64_neoverse_v1_initfn()
701 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_v1_initfn()
702 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_v1_initfn()
703 cpu->midr = 0x411FD402; /* r1p2 */ in aarch64_neoverse_v1_initfn()
704 cpu->revidr = 0; in aarch64_neoverse_v1_initfn()
717 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); in aarch64_neoverse_v1_initfn()
719 cpu->ccsidr[1] = cpu->ccsidr[0]; in aarch64_neoverse_v1_initfn()
721 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); in aarch64_neoverse_v1_initfn()
724 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_v1_initfn()
733 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_v1_initfn()
734 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_v1_initfn()
735 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_v1_initfn()
738 cpu->isar.id_aa64zfr0 = 0x0000100000100000; in aarch64_neoverse_v1_initfn()
739 cpu->sve_vq.supported = (1 << 0) /* 128bit */ in aarch64_neoverse_v1_initfn()
743 cpu->isar.reset_pmcr_el0 = 0x41213000; in aarch64_neoverse_v1_initfn()
753 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
754 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
757 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
758 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
761 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
762 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
765 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3,
766 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
769 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
770 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
773 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
774 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
777 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 4,
778 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
780 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
781 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
784 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
785 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
787 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0,
788 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
791 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1,
792 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
795 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2,
796 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
799 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
800 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
803 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
805 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
806 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
809 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
812 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
815 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
818 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
820 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0,
821 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
823 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
824 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
826 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
827 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
830 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
833 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
836 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
839 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
842 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
845 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
851 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
860 .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0,
861 .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 },
863 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0,
864 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
866 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1,
867 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
869 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2,
870 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
872 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0,
873 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
876 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
879 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
898 cpu->midr = 0x412FD471; /* r2p1 */ in aarch64_a710_initfn()
899 cpu->revidr = 0; in aarch64_a710_initfn()
900 cpu->isar.id_pfr0 = 0x21110131; in aarch64_a710_initfn()
901 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_a710_initfn()
902 cpu->isar.id_dfr0 = 0x16011099; in aarch64_a710_initfn()
903 cpu->id_afr0 = 0; in aarch64_a710_initfn()
904 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a710_initfn()
905 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a710_initfn()
906 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a710_initfn()
907 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a710_initfn()
908 cpu->isar.id_isar0 = 0x02101110; in aarch64_a710_initfn()
909 cpu->isar.id_isar1 = 0x13112111; in aarch64_a710_initfn()
910 cpu->isar.id_isar2 = 0x21232042; in aarch64_a710_initfn()
911 cpu->isar.id_isar3 = 0x01112131; in aarch64_a710_initfn()
912 cpu->isar.id_isar4 = 0x00010142; in aarch64_a710_initfn()
913 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ in aarch64_a710_initfn()
914 cpu->isar.id_mmfr4 = 0x21021110; in aarch64_a710_initfn()
915 cpu->isar.id_isar6 = 0x01111111; in aarch64_a710_initfn()
916 cpu->isar.mvfr0 = 0x10110222; in aarch64_a710_initfn()
917 cpu->isar.mvfr1 = 0x13211111; in aarch64_a710_initfn()
918 cpu->isar.mvfr2 = 0x00000043; in aarch64_a710_initfn()
919 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a710_initfn()
920 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ in aarch64_a710_initfn()
921 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; in aarch64_a710_initfn()
922 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ in aarch64_a710_initfn()
923 cpu->isar.id_aa64dfr0 = 0x000011f010305619ull; in aarch64_a710_initfn()
924 cpu->isar.id_aa64dfr1 = 0; in aarch64_a710_initfn()
925 cpu->id_aa64afr0 = 0; in aarch64_a710_initfn()
926 cpu->id_aa64afr1 = 0; in aarch64_a710_initfn()
927 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ in aarch64_a710_initfn()
928 cpu->isar.id_aa64isar1 = 0x0010111101211052ull; in aarch64_a710_initfn()
929 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; in aarch64_a710_initfn()
930 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a710_initfn()
931 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; in aarch64_a710_initfn()
932 cpu->clidr = 0x0000001482000023ull; in aarch64_a710_initfn()
934 cpu->ctr = 0x000000049444c004ull; in aarch64_a710_initfn()
936 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */ in aarch64_a710_initfn()
939 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ in aarch64_a710_initfn()
948 cpu->sve_vq.supported = 1 << 0; /* 128bit */ in aarch64_a710_initfn()
958 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); in aarch64_a710_initfn()
960 cpu->ccsidr[1] = cpu->ccsidr[0]; in aarch64_a710_initfn()
962 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); in aarch64_a710_initfn()
965 cpu->reset_sctlr = 0x30c50838; in aarch64_a710_initfn()
976 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0,
977 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
980 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
999 cpu->midr = 0x410FD493; /* r0p3 */ in aarch64_neoverse_n2_initfn()
1000 cpu->revidr = 0; in aarch64_neoverse_n2_initfn()
1001 cpu->isar.id_pfr0 = 0x21110131; in aarch64_neoverse_n2_initfn()
1002 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_n2_initfn()
1003 cpu->isar.id_dfr0 = 0x16011099; in aarch64_neoverse_n2_initfn()
1004 cpu->id_afr0 = 0; in aarch64_neoverse_n2_initfn()
1005 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_n2_initfn()
1006 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_n2_initfn()
1007 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_n2_initfn()
1008 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_n2_initfn()
1009 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_n2_initfn()
1010 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_n2_initfn()
1011 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_n2_initfn()
1012 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_n2_initfn()
1013 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_n2_initfn()
1014 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ in aarch64_neoverse_n2_initfn()
1015 cpu->isar.id_mmfr4 = 0x01021110; in aarch64_neoverse_n2_initfn()
1016 cpu->isar.id_isar6 = 0x01111111; in aarch64_neoverse_n2_initfn()
1017 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_n2_initfn()
1018 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_n2_initfn()
1019 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_n2_initfn()
1020 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_n2_initfn()
1021 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ in aarch64_neoverse_n2_initfn()
1022 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; in aarch64_neoverse_n2_initfn()
1023 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ in aarch64_neoverse_n2_initfn()
1024 cpu->isar.id_aa64dfr0 = 0x000011f210305619ull; in aarch64_neoverse_n2_initfn()
1025 cpu->isar.id_aa64dfr1 = 0; in aarch64_neoverse_n2_initfn()
1026 cpu->id_aa64afr0 = 0; in aarch64_neoverse_n2_initfn()
1027 cpu->id_aa64afr1 = 0; in aarch64_neoverse_n2_initfn()
1028 cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */ in aarch64_neoverse_n2_initfn()
1029 cpu->isar.id_aa64isar1 = 0x0011111101211052ull; in aarch64_neoverse_n2_initfn()
1030 cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull; in aarch64_neoverse_n2_initfn()
1031 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_n2_initfn()
1032 cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull; in aarch64_neoverse_n2_initfn()
1033 cpu->clidr = 0x0000001482000023ull; in aarch64_neoverse_n2_initfn()
1035 cpu->ctr = 0x00000004b444c004ull; in aarch64_neoverse_n2_initfn()
1037 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */ in aarch64_neoverse_n2_initfn()
1040 cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */ in aarch64_neoverse_n2_initfn()
1049 cpu->sve_vq.supported = 1 << 0; /* 128bit */ in aarch64_neoverse_n2_initfn()
1059 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); in aarch64_neoverse_n2_initfn()
1061 cpu->ccsidr[1] = cpu->ccsidr[0]; in aarch64_neoverse_n2_initfn()
1063 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); in aarch64_neoverse_n2_initfn()
1065 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_n2_initfn()
1102 * An IMPLEMENTER field of 0 means "reserved for software use"; in aarch64_max_tcg_initfn()
1103 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers in aarch64_max_tcg_initfn()
1110 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); in aarch64_max_tcg_initfn()
1111 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); in aarch64_max_tcg_initfn()
1113 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); in aarch64_max_tcg_initfn()
1114 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); in aarch64_max_tcg_initfn()
1122 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); in aarch64_max_tcg_initfn()
1123 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); in aarch64_max_tcg_initfn()
1189 * Begin with full support for MTE. This will be downgraded to MTE=0 in aarch64_max_tcg_initfn()
1194 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ in aarch64_max_tcg_initfn()
1196 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ in aarch64_max_tcg_initfn()
1266 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ in aarch64_max_tcg_initfn()
1268 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ in aarch64_max_tcg_initfn()
1280 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ in aarch64_max_tcg_initfn()
1285 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); in aarch64_max_tcg_initfn()
1315 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { in aarch64_cpu_register_types()