92     /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */  in aa32_max_features()
93     t = 0x00008000;  in aa32_max_features()
102     t = 0;  in aa32_max_features()
106     t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);  in aa32_max_features()
109     t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);  in aa32_max_features()
110     t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);  in aa32_max_features()
114     t = 0;  in aa32_max_features()
134     cpu->midr = 0x41069265;  in arm926_initfn()
135     cpu->reset_fpsid = 0x41011090;  in arm926_initfn()
136     cpu->ctr = 0x1dd20d2;  in arm926_initfn()
137     cpu->reset_sctlr = 0x00090078;  in arm926_initfn()
161     cpu->midr = 0x41059461;  in arm946_initfn()
162     cpu->ctr = 0x0f004006;  in arm946_initfn()
163     cpu->reset_sctlr = 0x00000078;  in arm946_initfn()
175     cpu->midr = 0x4106a262;  in arm1026_initfn()
176     cpu->reset_fpsid = 0x410110a0;  in arm1026_initfn()
177     cpu->ctr = 0x1dd20d2;  in arm1026_initfn()
178     cpu->reset_sctlr = 0x00090078;  in arm1026_initfn()
195         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */  in arm1026_initfn()
197             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,  in arm1026_initfn()
200             .resetvalue = 0  in arm1026_initfn()
223     cpu->midr = 0x4107b362;  in arm1136_r2_initfn()
224     cpu->reset_fpsid = 0x410120b4;  in arm1136_r2_initfn()
225     cpu->isar.mvfr0 = 0x11111111;  in arm1136_r2_initfn()
226     cpu->isar.mvfr1 = 0x00000000;  in arm1136_r2_initfn()
227     cpu->ctr = 0x1dd20d2;  in arm1136_r2_initfn()
228     cpu->reset_sctlr = 0x00050078;  in arm1136_r2_initfn()
229     cpu->isar.id_pfr0 = 0x111;  in arm1136_r2_initfn()
230     cpu->isar.id_pfr1 = 0x1;  in arm1136_r2_initfn()
231     cpu->isar.id_dfr0 = 0x2;  in arm1136_r2_initfn()
232     cpu->id_afr0 = 0x3;  in arm1136_r2_initfn()
233     cpu->isar.id_mmfr0 = 0x01130003;  in arm1136_r2_initfn()
234     cpu->isar.id_mmfr1 = 0x10030302;  in arm1136_r2_initfn()
235     cpu->isar.id_mmfr2 = 0x01222110;  in arm1136_r2_initfn()
236     cpu->isar.id_isar0 = 0x00140011;  in arm1136_r2_initfn()
237     cpu->isar.id_isar1 = 0x12002111;  in arm1136_r2_initfn()
238     cpu->isar.id_isar2 = 0x11231111;  in arm1136_r2_initfn()
239     cpu->isar.id_isar3 = 0x01102131;  in arm1136_r2_initfn()
240     cpu->isar.id_isar4 = 0x141;  in arm1136_r2_initfn()
254     cpu->midr = 0x4117b363;  in arm1136_initfn()
255     cpu->reset_fpsid = 0x410120b4;  in arm1136_initfn()
256     cpu->isar.mvfr0 = 0x11111111;  in arm1136_initfn()
257     cpu->isar.mvfr1 = 0x00000000;  in arm1136_initfn()
258     cpu->ctr = 0x1dd20d2;  in arm1136_initfn()
259     cpu->reset_sctlr = 0x00050078;  in arm1136_initfn()
260     cpu->isar.id_pfr0 = 0x111;  in arm1136_initfn()
261     cpu->isar.id_pfr1 = 0x1;  in arm1136_initfn()
262     cpu->isar.id_dfr0 = 0x2;  in arm1136_initfn()
263     cpu->id_afr0 = 0x3;  in arm1136_initfn()
264     cpu->isar.id_mmfr0 = 0x01130003;  in arm1136_initfn()
265     cpu->isar.id_mmfr1 = 0x10030302;  in arm1136_initfn()
266     cpu->isar.id_mmfr2 = 0x01222110;  in arm1136_initfn()
267     cpu->isar.id_isar0 = 0x00140011;  in arm1136_initfn()
268     cpu->isar.id_isar1 = 0x12002111;  in arm1136_initfn()
269     cpu->isar.id_isar2 = 0x11231111;  in arm1136_initfn()
270     cpu->isar.id_isar3 = 0x01102131;  in arm1136_initfn()
271     cpu->isar.id_isar4 = 0x141;  in arm1136_initfn()
286     cpu->midr = 0x410fb767;  in arm1176_initfn()
287     cpu->reset_fpsid = 0x410120b5;  in arm1176_initfn()
288     cpu->isar.mvfr0 = 0x11111111;  in arm1176_initfn()
289     cpu->isar.mvfr1 = 0x00000000;  in arm1176_initfn()
290     cpu->ctr = 0x1dd20d2;  in arm1176_initfn()
291     cpu->reset_sctlr = 0x00050078;  in arm1176_initfn()
292     cpu->isar.id_pfr0 = 0x111;  in arm1176_initfn()
293     cpu->isar.id_pfr1 = 0x11;  in arm1176_initfn()
294     cpu->isar.id_dfr0 = 0x33;  in arm1176_initfn()
295     cpu->id_afr0 = 0;  in arm1176_initfn()
296     cpu->isar.id_mmfr0 = 0x01130003;  in arm1176_initfn()
297     cpu->isar.id_mmfr1 = 0x10030302;  in arm1176_initfn()
298     cpu->isar.id_mmfr2 = 0x01222100;  in arm1176_initfn()
299     cpu->isar.id_isar0 = 0x0140011;  in arm1176_initfn()
300     cpu->isar.id_isar1 = 0x12002111;  in arm1176_initfn()
301     cpu->isar.id_isar2 = 0x11231121;  in arm1176_initfn()
302     cpu->isar.id_isar3 = 0x01102131;  in arm1176_initfn()
303     cpu->isar.id_isar4 = 0x01141;  in arm1176_initfn()
316     cpu->midr = 0x410fb022;  in arm11mpcore_initfn()
317     cpu->reset_fpsid = 0x410120b4;  in arm11mpcore_initfn()
318     cpu->isar.mvfr0 = 0x11111111;  in arm11mpcore_initfn()
319     cpu->isar.mvfr1 = 0x00000000;  in arm11mpcore_initfn()
320     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */  in arm11mpcore_initfn()
321     cpu->isar.id_pfr0 = 0x111;  in arm11mpcore_initfn()
322     cpu->isar.id_pfr1 = 0x1;  in arm11mpcore_initfn()
323     cpu->isar.id_dfr0 = 0;  in arm11mpcore_initfn()
324     cpu->id_afr0 = 0x2;  in arm11mpcore_initfn()
325     cpu->isar.id_mmfr0 = 0x01100103;  in arm11mpcore_initfn()
326     cpu->isar.id_mmfr1 = 0x10020302;  in arm11mpcore_initfn()
327     cpu->isar.id_mmfr2 = 0x01222000;  in arm11mpcore_initfn()
328     cpu->isar.id_isar0 = 0x00100011;  in arm11mpcore_initfn()
329     cpu->isar.id_isar1 = 0x12002111;  in arm11mpcore_initfn()
330     cpu->isar.id_isar2 = 0x11221011;  in arm11mpcore_initfn()
331     cpu->isar.id_isar3 = 0x01102131;  in arm11mpcore_initfn()
332     cpu->isar.id_isar4 = 0x141;  in arm11mpcore_initfn()
337     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
338       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
339     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
340       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
354     cpu->midr = 0x410fc080;  in cortex_a8_initfn()
355     cpu->reset_fpsid = 0x410330c0;  in cortex_a8_initfn()
356     cpu->isar.mvfr0 = 0x11110222;  in cortex_a8_initfn()
357     cpu->isar.mvfr1 = 0x00011111;  in cortex_a8_initfn()
358     cpu->ctr = 0x82048004;  in cortex_a8_initfn()
359     cpu->reset_sctlr = 0x00c50078;  in cortex_a8_initfn()
360     cpu->isar.id_pfr0 = 0x1031;  in cortex_a8_initfn()
361     cpu->isar.id_pfr1 = 0x11;  in cortex_a8_initfn()
362     cpu->isar.id_dfr0 = 0x400;  in cortex_a8_initfn()
363     cpu->id_afr0 = 0;  in cortex_a8_initfn()
364     cpu->isar.id_mmfr0 = 0x31100003;  in cortex_a8_initfn()
365     cpu->isar.id_mmfr1 = 0x20000000;  in cortex_a8_initfn()
366     cpu->isar.id_mmfr2 = 0x01202000;  in cortex_a8_initfn()
367     cpu->isar.id_mmfr3 = 0x11;  in cortex_a8_initfn()
368     cpu->isar.id_isar0 = 0x00101111;  in cortex_a8_initfn()
369     cpu->isar.id_isar1 = 0x12112111;  in cortex_a8_initfn()
370     cpu->isar.id_isar2 = 0x21232031;  in cortex_a8_initfn()
371     cpu->isar.id_isar3 = 0x11112131;  in cortex_a8_initfn()
372     cpu->isar.id_isar4 = 0x00111142;  in cortex_a8_initfn()
373     cpu->isar.dbgdidr = 0x15141000;  in cortex_a8_initfn()
375     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */  in cortex_a8_initfn()
376     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */  in cortex_a8_initfn()
377     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */  in cortex_a8_initfn()
379     cpu->isar.reset_pmcr_el0 = 0x41002000;  in cortex_a8_initfn()
386      * default to 0 and set by private hook
388     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
389       .access = PL1_RW, .resetvalue = 0,
391     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
392       .access = PL1_RW, .resetvalue = 0,
394     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
395       .access = PL1_RW, .resetvalue = 0,
397     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
398       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
401       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
403       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
405       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
407       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
409       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
429     cpu->midr = 0x410fc090;  in cortex_a9_initfn()
430     cpu->reset_fpsid = 0x41033090;  in cortex_a9_initfn()
431     cpu->isar.mvfr0 = 0x11110222;  in cortex_a9_initfn()
432     cpu->isar.mvfr1 = 0x01111111;  in cortex_a9_initfn()
433     cpu->ctr = 0x80038003;  in cortex_a9_initfn()
434     cpu->reset_sctlr = 0x00c50078;  in cortex_a9_initfn()
435     cpu->isar.id_pfr0 = 0x1031;  in cortex_a9_initfn()
436     cpu->isar.id_pfr1 = 0x11;  in cortex_a9_initfn()
437     cpu->isar.id_dfr0 = 0x000;  in cortex_a9_initfn()
438     cpu->id_afr0 = 0;  in cortex_a9_initfn()
439     cpu->isar.id_mmfr0 = 0x00100103;  in cortex_a9_initfn()
440     cpu->isar.id_mmfr1 = 0x20000000;  in cortex_a9_initfn()
441     cpu->isar.id_mmfr2 = 0x01230000;  in cortex_a9_initfn()
442     cpu->isar.id_mmfr3 = 0x00002111;  in cortex_a9_initfn()
443     cpu->isar.id_isar0 = 0x00101111;  in cortex_a9_initfn()
444     cpu->isar.id_isar1 = 0x13112111;  in cortex_a9_initfn()
445     cpu->isar.id_isar2 = 0x21232041;  in cortex_a9_initfn()
446     cpu->isar.id_isar3 = 0x11112131;  in cortex_a9_initfn()
447     cpu->isar.id_isar4 = 0x00111142;  in cortex_a9_initfn()
448     cpu->isar.dbgdidr = 0x35141000;  in cortex_a9_initfn()
450     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */  in cortex_a9_initfn()
451     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */  in cortex_a9_initfn()
452     cpu->isar.reset_pmcr_el0 = 0x41093000;  in cortex_a9_initfn()
471     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
472       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
475     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
476       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
494     cpu->midr = 0x410fc075;  in cortex_a7_initfn()
495     cpu->reset_fpsid = 0x41023075;  in cortex_a7_initfn()
496     cpu->isar.mvfr0 = 0x10110222;  in cortex_a7_initfn()
497     cpu->isar.mvfr1 = 0x11111111;  in cortex_a7_initfn()
498     cpu->ctr = 0x84448003;  in cortex_a7_initfn()
499     cpu->reset_sctlr = 0x00c50078;  in cortex_a7_initfn()
500     cpu->isar.id_pfr0 = 0x00001131;  in cortex_a7_initfn()
501     cpu->isar.id_pfr1 = 0x00011011;  in cortex_a7_initfn()
502     cpu->isar.id_dfr0 = 0x02010555;  in cortex_a7_initfn()
503     cpu->id_afr0 = 0x00000000;  in cortex_a7_initfn()
504     cpu->isar.id_mmfr0 = 0x10101105;  in cortex_a7_initfn()
505     cpu->isar.id_mmfr1 = 0x40000000;  in cortex_a7_initfn()
506     cpu->isar.id_mmfr2 = 0x01240000;  in cortex_a7_initfn()
507     cpu->isar.id_mmfr3 = 0x02102211;  in cortex_a7_initfn()
509      * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but  in cortex_a7_initfn()
510      * table 4-41 gives 0x02101110, which includes the arm div insns.  in cortex_a7_initfn()
512     cpu->isar.id_isar0 = 0x02101110;  in cortex_a7_initfn()
513     cpu->isar.id_isar1 = 0x13112111;  in cortex_a7_initfn()
514     cpu->isar.id_isar2 = 0x21232041;  in cortex_a7_initfn()
515     cpu->isar.id_isar3 = 0x11112131;  in cortex_a7_initfn()
516     cpu->isar.id_isar4 = 0x10011142;  in cortex_a7_initfn()
517     cpu->isar.dbgdidr = 0x3515f005;  in cortex_a7_initfn()
518     cpu->isar.dbgdevid = 0x01110f13;  in cortex_a7_initfn()
519     cpu->isar.dbgdevid1 = 0x1;  in cortex_a7_initfn()
520     cpu->clidr = 0x0a200023;  in cortex_a7_initfn()
521     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */  in cortex_a7_initfn()
522     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */  in cortex_a7_initfn()
523     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */  in cortex_a7_initfn()
524     cpu->isar.reset_pmcr_el0 = 0x41072000;  in cortex_a7_initfn()
544     cpu->midr = 0x414fc0f0;  in cortex_a15_initfn()
545     cpu->revidr = 0x0;  in cortex_a15_initfn()
546     cpu->reset_fpsid = 0x410430f0;  in cortex_a15_initfn()
547     cpu->isar.mvfr0 = 0x10110222;  in cortex_a15_initfn()
548     cpu->isar.mvfr1 = 0x11111111;  in cortex_a15_initfn()
549     cpu->ctr = 0x8444c004;  in cortex_a15_initfn()
550     cpu->reset_sctlr = 0x00c50078;  in cortex_a15_initfn()
551     cpu->isar.id_pfr0 = 0x00001131;  in cortex_a15_initfn()
552     cpu->isar.id_pfr1 = 0x00011011;  in cortex_a15_initfn()
553     cpu->isar.id_dfr0 = 0x02010555;  in cortex_a15_initfn()
554     cpu->id_afr0 = 0x00000000;  in cortex_a15_initfn()
555     cpu->isar.id_mmfr0 = 0x10201105;  in cortex_a15_initfn()
556     cpu->isar.id_mmfr1 = 0x20000000;  in cortex_a15_initfn()
557     cpu->isar.id_mmfr2 = 0x01240000;  in cortex_a15_initfn()
558     cpu->isar.id_mmfr3 = 0x02102211;  in cortex_a15_initfn()
559     cpu->isar.id_isar0 = 0x02101110;  in cortex_a15_initfn()
560     cpu->isar.id_isar1 = 0x13112111;  in cortex_a15_initfn()
561     cpu->isar.id_isar2 = 0x21232041;  in cortex_a15_initfn()
562     cpu->isar.id_isar3 = 0x11112131;  in cortex_a15_initfn()
563     cpu->isar.id_isar4 = 0x10011142;  in cortex_a15_initfn()
564     cpu->isar.dbgdidr = 0x3515f021;  in cortex_a15_initfn()
565     cpu->isar.dbgdevid = 0x01110f13;  in cortex_a15_initfn()
566     cpu->isar.dbgdevid1 = 0x0;  in cortex_a15_initfn()
567     cpu->clidr = 0x0a200023;  in cortex_a15_initfn()
568     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */  in cortex_a15_initfn()
569     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */  in cortex_a15_initfn()
570     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */  in cortex_a15_initfn()
571     cpu->isar.reset_pmcr_el0 = 0x410F3000;  in cortex_a15_initfn()
577     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
579     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
581     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
582       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
593     cpu->midr = 0x411fc153; /* r1p3 */  in cortex_r5_initfn()
594     cpu->isar.id_pfr0 = 0x0131;  in cortex_r5_initfn()
595     cpu->isar.id_pfr1 = 0x001;  in cortex_r5_initfn()
596     cpu->isar.id_dfr0 = 0x010400;  in cortex_r5_initfn()
597     cpu->id_afr0 = 0x0;  in cortex_r5_initfn()
598     cpu->isar.id_mmfr0 = 0x0210030;  in cortex_r5_initfn()
599     cpu->isar.id_mmfr1 = 0x00000000;  in cortex_r5_initfn()
600     cpu->isar.id_mmfr2 = 0x01200000;  in cortex_r5_initfn()
601     cpu->isar.id_mmfr3 = 0x0211;  in cortex_r5_initfn()
602     cpu->isar.id_isar0 = 0x02101111;  in cortex_r5_initfn()
603     cpu->isar.id_isar1 = 0x13112111;  in cortex_r5_initfn()
604     cpu->isar.id_isar2 = 0x21232141;  in cortex_r5_initfn()
605     cpu->isar.id_isar3 = 0x01112131;  in cortex_r5_initfn()
606     cpu->isar.id_isar4 = 0x0010142;  in cortex_r5_initfn()
607     cpu->isar.id_isar5 = 0x0;  in cortex_r5_initfn()
608     cpu->isar.id_isar6 = 0x0;  in cortex_r5_initfn()
611     cpu->isar.reset_pmcr_el0 = 0x41151800;  in cortex_r5_initfn()
616     { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
617       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
619       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
620       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
622       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
623       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
625       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
626       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
628       .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
629       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
632       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
635       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
637       .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
638       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
640       .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
641       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
643       .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
644       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
646       .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
647       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
649       .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
650       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
653       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
656       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
659       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
661       .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
662       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
664       .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
665       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
667       .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
668       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
671       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
673       .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
674       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
677       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
680       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
683       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
685       .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
686       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
689       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
691       .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
692       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
694       .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
695       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
697       .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
698       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
700       .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
701       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
703       .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
704       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
706       .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
707       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
710       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
712       .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
713       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
716       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
732     cpu->midr = 0x411fd133; /* r1p3 */  in cortex_r52_initfn()
733     cpu->revidr = 0x00000000;  in cortex_r52_initfn()
734     cpu->reset_fpsid = 0x41034023;  in cortex_r52_initfn()
735     cpu->isar.mvfr0 = 0x10110222;  in cortex_r52_initfn()
736     cpu->isar.mvfr1 = 0x12111111;  in cortex_r52_initfn()
737     cpu->isar.mvfr2 = 0x00000043;  in cortex_r52_initfn()
738     cpu->ctr = 0x8144c004;  in cortex_r52_initfn()
739     cpu->reset_sctlr = 0x30c50838;  in cortex_r52_initfn()
740     cpu->isar.id_pfr0 = 0x00000131;  in cortex_r52_initfn()
741     cpu->isar.id_pfr1 = 0x10111001;  in cortex_r52_initfn()
742     cpu->isar.id_dfr0 = 0x03010006;  in cortex_r52_initfn()
743     cpu->id_afr0 = 0x00000000;  in cortex_r52_initfn()
744     cpu->isar.id_mmfr0 = 0x00211040;  in cortex_r52_initfn()
745     cpu->isar.id_mmfr1 = 0x40000000;  in cortex_r52_initfn()
746     cpu->isar.id_mmfr2 = 0x01200000;  in cortex_r52_initfn()
747     cpu->isar.id_mmfr3 = 0xf0102211;  in cortex_r52_initfn()
748     cpu->isar.id_mmfr4 = 0x00000010;  in cortex_r52_initfn()
749     cpu->isar.id_isar0 = 0x02101110;  in cortex_r52_initfn()
750     cpu->isar.id_isar1 = 0x13112111;  in cortex_r52_initfn()
751     cpu->isar.id_isar2 = 0x21232142;  in cortex_r52_initfn()
752     cpu->isar.id_isar3 = 0x01112131;  in cortex_r52_initfn()
753     cpu->isar.id_isar4 = 0x00010142;  in cortex_r52_initfn()
754     cpu->isar.id_isar5 = 0x00010001;  in cortex_r52_initfn()
755     cpu->isar.dbgdidr = 0x77168000;  in cortex_r52_initfn()
756     cpu->clidr = (1 << 27) | (1 << 24) | 0x3;  in cortex_r52_initfn()
757     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */  in cortex_r52_initfn()
758     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */  in cortex_r52_initfn()
771     cpu->isar.mvfr0 = 0x10110221;  in cortex_r5f_initfn()
772     cpu->isar.mvfr1 = 0x00000011;  in cortex_r5f_initfn()
781     cpu->ctr = 0x5109149;  in ti925t_initfn()
782     cpu->reset_sctlr = 0x00000070;  in ti925t_initfn()
792     cpu->midr = 0x4401A11B;  in sa1100_initfn()
793     cpu->reset_sctlr = 0x00000070;  in sa1100_initfn()
801     cpu->midr = 0x6901B119;  in sa1110_initfn()
802     cpu->reset_sctlr = 0x00000070;  in sa1110_initfn()
812     cpu->midr = 0x69052100;  in pxa250_initfn()
813     cpu->ctr = 0xd172172;  in pxa250_initfn()
814     cpu->reset_sctlr = 0x00000078;  in pxa250_initfn()
824     cpu->midr = 0x69052d00;  in pxa255_initfn()
825     cpu->ctr = 0xd172172;  in pxa255_initfn()
826     cpu->reset_sctlr = 0x00000078;  in pxa255_initfn()
836     cpu->midr = 0x69052903;  in pxa260_initfn()
837     cpu->ctr = 0xd172172;  in pxa260_initfn()
838     cpu->reset_sctlr = 0x00000078;  in pxa260_initfn()
848     cpu->midr = 0x69052d05;  in pxa261_initfn()
849     cpu->ctr = 0xd172172;  in pxa261_initfn()
850     cpu->reset_sctlr = 0x00000078;  in pxa261_initfn()
860     cpu->midr = 0x69052d06;  in pxa262_initfn()
861     cpu->ctr = 0xd172172;  in pxa262_initfn()
862     cpu->reset_sctlr = 0x00000078;  in pxa262_initfn()
873     cpu->midr = 0x69054110;  in pxa270a0_initfn()
874     cpu->ctr = 0xd172172;  in pxa270a0_initfn()
875     cpu->reset_sctlr = 0x00000078;  in pxa270a0_initfn()
886     cpu->midr = 0x69054111;  in pxa270a1_initfn()
887     cpu->ctr = 0xd172172;  in pxa270a1_initfn()
888     cpu->reset_sctlr = 0x00000078;  in pxa270a1_initfn()
899     cpu->midr = 0x69054112;  in pxa270b0_initfn()
900     cpu->ctr = 0xd172172;  in pxa270b0_initfn()
901     cpu->reset_sctlr = 0x00000078;  in pxa270b0_initfn()
912     cpu->midr = 0x69054113;  in pxa270b1_initfn()
913     cpu->ctr = 0xd172172;  in pxa270b1_initfn()
914     cpu->reset_sctlr = 0x00000078;  in pxa270b1_initfn()
925     cpu->midr = 0x69054114;  in pxa270c0_initfn()
926     cpu->ctr = 0xd172172;  in pxa270c0_initfn()
927     cpu->reset_sctlr = 0x00000078;  in pxa270c0_initfn()
938     cpu->midr = 0x69054117;  in pxa270c5_initfn()
939     cpu->ctr = 0xd172172;  in pxa270c5_initfn()
940     cpu->reset_sctlr = 0x00000078;  in pxa270c5_initfn()
963     cpu->midr = 0x411fd070;  in arm_max_initfn()
964     cpu->revidr = 0x00000000;  in arm_max_initfn()
965     cpu->reset_fpsid = 0x41034070;  in arm_max_initfn()
966     cpu->isar.mvfr0 = 0x10110222;  in arm_max_initfn()
967     cpu->isar.mvfr1 = 0x12111111;  in arm_max_initfn()
968     cpu->isar.mvfr2 = 0x00000043;  in arm_max_initfn()
969     cpu->ctr = 0x8444c004;  in arm_max_initfn()
970     cpu->reset_sctlr = 0x00c50838;  in arm_max_initfn()
971     cpu->isar.id_pfr0 = 0x00000131;  in arm_max_initfn()
972     cpu->isar.id_pfr1 = 0x00011011;  in arm_max_initfn()
973     cpu->isar.id_dfr0 = 0x03010066;  in arm_max_initfn()
974     cpu->id_afr0 = 0x00000000;  in arm_max_initfn()
975     cpu->isar.id_mmfr0 = 0x10101105;  in arm_max_initfn()
976     cpu->isar.id_mmfr1 = 0x40000000;  in arm_max_initfn()
977     cpu->isar.id_mmfr2 = 0x01260000;  in arm_max_initfn()
978     cpu->isar.id_mmfr3 = 0x02102211;  in arm_max_initfn()
979     cpu->isar.id_isar0 = 0x02101110;  in arm_max_initfn()
980     cpu->isar.id_isar1 = 0x13112111;  in arm_max_initfn()
981     cpu->isar.id_isar2 = 0x21232042;  in arm_max_initfn()
982     cpu->isar.id_isar3 = 0x01112131;  in arm_max_initfn()
983     cpu->isar.id_isar4 = 0x00011142;  in arm_max_initfn()
984     cpu->isar.id_isar5 = 0x00011121;  in arm_max_initfn()
985     cpu->isar.id_isar6 = 0;  in arm_max_initfn()
986     cpu->isar.reset_pmcr_el0 = 0x41013000;  in arm_max_initfn()
987     cpu->clidr = 0x0a200023;  in arm_max_initfn()
988     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */  in arm_max_initfn()
989     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */  in arm_max_initfn()
990     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */  in arm_max_initfn()
1061     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {  in arm_tcg_cpu_register_types()