Lines Matching refs:fi
80 ARMMMUFaultInfo *fi);
86 ARMMMUFaultInfo *fi);
286 ARMMMUFaultInfo *fi) in granule_protection_check() argument
458 fi->gpcf = GPCF_Fail; in granule_protection_check()
461 fi->gpcf = GPCF_EABT; in granule_protection_check()
464 fi->gpcf = GPCF_AddressSize; in granule_protection_check()
467 fi->gpcf = GPCF_Walk; in granule_protection_check()
469 fi->level = level; in granule_protection_check()
470 fi->paddr = paddress; in granule_protection_check()
471 fi->paddr_space = pspace; in granule_protection_check()
545 hwaddr addr, ARMMMUFaultInfo *fi) in S1_ptw_translate() argument
567 if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { in S1_ptw_translate()
581 env->tlb_fi = fi; in S1_ptw_translate()
607 fi->type = ARMFault_Permission; in S1_ptw_translate()
608 fi->s2addr = addr; in S1_ptw_translate()
609 fi->stage2 = true; in S1_ptw_translate()
610 fi->s1ptw = true; in S1_ptw_translate()
611 fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); in S1_ptw_translate()
620 assert(fi->type != ARMFault_None); in S1_ptw_translate()
621 if (fi->type == ARMFault_GPCFOnOutput) { in S1_ptw_translate()
622 fi->type = ARMFault_GPCFOnWalk; in S1_ptw_translate()
624 fi->s2addr = addr; in S1_ptw_translate()
625 fi->stage2 = regime_is_stage2(s2_mmu_idx); in S1_ptw_translate()
626 fi->s1ptw = fi->stage2; in S1_ptw_translate()
627 fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); in S1_ptw_translate()
633 ARMMMUFaultInfo *fi) in arm_ldl_ptw() argument
662 fi->type = ARMFault_SyncExternalOnWalk; in arm_ldl_ptw()
663 fi->ea = arm_extabort_type(result); in arm_ldl_ptw()
671 ARMMMUFaultInfo *fi) in arm_ldq_ptw() argument
708 fi->type = ARMFault_SyncExternalOnWalk; in arm_ldq_ptw()
709 fi->ea = arm_extabort_type(result); in arm_ldq_ptw()
718 ARMMMUFaultInfo *fi) in arm_casq_ptw() argument
741 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
742 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
751 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
752 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
763 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
764 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
773 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
774 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
796 env->tlb_fi = fi; in arm_casq_ptw()
810 assert(fi->type != ARMFault_None); in arm_casq_ptw()
811 fi->s2addr = ptw->out_virt; in arm_casq_ptw()
812 fi->stage2 = true; in arm_casq_ptw()
813 fi->s1ptw = true; in arm_casq_ptw()
814 fi->s1ns = fault_s1ns(ptw->in_space, ptw->in_ptw_idx); in arm_casq_ptw()
994 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr_v5() argument
1010 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1013 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v5()
1016 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v5()
1017 if (fi->type != ARMFault_None) { in get_phys_addr_v5()
1030 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1037 fi->type = ARMFault_Domain; in get_phys_addr_v5()
1054 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v5()
1057 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v5()
1058 if (fi->type != ARMFault_None) { in get_phys_addr_v5()
1063 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1087 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1105 fi->type = ARMFault_Permission; in get_phys_addr_v5()
1111 fi->domain = domain; in get_phys_addr_v5()
1112 fi->level = level; in get_phys_addr_v5()
1118 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr_v6() argument
1140 fi->type = ARMFault_Translation; in get_phys_addr_v6()
1143 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v6()
1146 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v6()
1147 if (fi->type != ARMFault_None) { in get_phys_addr_v6()
1155 fi->type = ARMFault_Translation; in get_phys_addr_v6()
1173 fi->type = ARMFault_Domain; in get_phys_addr_v6()
1199 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v6()
1202 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v6()
1203 if (fi->type != ARMFault_None) { in get_phys_addr_v6()
1209 fi->type = ARMFault_Translation; in get_phys_addr_v6()
1233 fi->type = ARMFault_Permission; in get_phys_addr_v6()
1242 fi->type = ARMFault_AccessFlag; in get_phys_addr_v6()
1256 fi->type = ARMFault_Permission; in get_phys_addr_v6()
1264 fi->type = ARMFault_Permission; in get_phys_addr_v6()
1279 fi->domain = domain; in get_phys_addr_v6()
1280 fi->level = level; in get_phys_addr_v6()
1678 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr_lpae() argument
1834 fi->type = ARMFault_AddressSize; in get_phys_addr_lpae()
1885 if (!S1_ptw_translate(env, ptw, descaddr, fi)) { in get_phys_addr_lpae()
1888 descriptor = arm_ldq_ptw(env, ptw, fi); in get_phys_addr_lpae()
1889 if (fi->type != ARMFault_None) { in get_phys_addr_lpae()
1917 fi->type = ARMFault_AddressSize; in get_phys_addr_lpae()
1959 fi->type = ARMFault_AccessFlag; in get_phys_addr_lpae()
2092 fi->type = ARMFault_Permission; in get_phys_addr_lpae()
2098 new_descriptor = arm_casq_ptw(env, descriptor, new_descriptor, ptw, fi); in get_phys_addr_lpae()
2099 if (fi->type != ARMFault_None) { in get_phys_addr_lpae()
2179 fi->type = ARMFault_Translation; in get_phys_addr_lpae()
2181 if (fi->s1ptw) { in get_phys_addr_lpae()
2183 assert(fi->stage2); in get_phys_addr_lpae()
2185 fi->level = level; in get_phys_addr_lpae()
2186 fi->stage2 = regime_is_stage2(mmu_idx); in get_phys_addr_lpae()
2188 fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); in get_phys_addr_lpae()
2197 ARMMMUFaultInfo *fi) in get_phys_addr_pmsav5() argument
2227 fi->type = ARMFault_Background; in get_phys_addr_pmsav5()
2239 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2240 fi->level = 1; in get_phys_addr_pmsav5()
2244 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2245 fi->level = 1; in get_phys_addr_pmsav5()
2261 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2262 fi->level = 1; in get_phys_addr_pmsav5()
2272 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2273 fi->level = 1; in get_phys_addr_pmsav5()
2365 ARMMMUFaultInfo *fi) in get_phys_addr_pmsav7() argument
2475 fi->type = ARMFault_Background; in get_phys_addr_pmsav7()
2548 fi->type = ARMFault_Permission; in get_phys_addr_pmsav7()
2549 fi->level = 1; in get_phys_addr_pmsav7()
2576 ARMMMUFaultInfo *fi, uint32_t *mregion) in pmsav8_mpu_lookup() argument
2611 fi->stage2 = true; in pmsav8_mpu_lookup()
2636 fi->level = 0; in pmsav8_mpu_lookup()
2683 fi->type = ARMFault_Permission; in pmsav8_mpu_lookup()
2685 fi->level = 1; in pmsav8_mpu_lookup()
2697 fi->type = ARMFault_Background; in pmsav8_mpu_lookup()
2699 fi->type = ARMFault_Permission; in pmsav8_mpu_lookup()
2759 fi->type = ARMFault_Permission; in pmsav8_mpu_lookup()
2761 fi->level = 1; in pmsav8_mpu_lookup()
2896 ARMMMUFaultInfo *fi) in get_phys_addr_pmsav8() argument
2927 fi->type = ARMFault_QEMU_NSCExec; in get_phys_addr_pmsav8()
2929 fi->type = ARMFault_QEMU_SFault; in get_phys_addr_pmsav8()
2956 fi->type = ARMFault_QEMU_SFault; in get_phys_addr_pmsav8()
2966 result, fi, NULL); in get_phys_addr_pmsav8()
3208 ARMMMUFaultInfo *fi) in get_phys_addr_disabled() argument
3239 fi->type = ARMFault_AddressSize; in get_phys_addr_disabled()
3240 fi->level = 0; in get_phys_addr_disabled()
3241 fi->stage2 = false; in get_phys_addr_disabled()
3291 ARMMMUFaultInfo *fi) in get_phys_addr_twostage() argument
3301 ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); in get_phys_addr_twostage()
3327 ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); in get_phys_addr_twostage()
3328 fi->s2addr = ipa; in get_phys_addr_twostage()
3396 ARMMMUFaultInfo *fi) in get_phys_addr_nogpc() argument
3416 result, fi); in get_phys_addr_nogpc()
3457 result, fi); in get_phys_addr_nogpc()
3489 result, fi); in get_phys_addr_nogpc()
3493 result, fi); in get_phys_addr_nogpc()
3497 result, fi); in get_phys_addr_nogpc()
3516 result, fi); in get_phys_addr_nogpc()
3520 return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); in get_phys_addr_nogpc()
3523 return get_phys_addr_v6(env, ptw, address, access_type, result, fi); in get_phys_addr_nogpc()
3525 return get_phys_addr_v5(env, ptw, address, access_type, result, fi); in get_phys_addr_nogpc()
3533 ARMMMUFaultInfo *fi) in get_phys_addr_gpc() argument
3535 if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { in get_phys_addr_gpc()
3539 result->f.attrs.space, fi)) { in get_phys_addr_gpc()
3540 fi->type = ARMFault_GPCFOnOutput; in get_phys_addr_gpc()
3550 ARMMMUFaultInfo *fi) in get_phys_addr_with_space_nogpc() argument
3556 return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); in get_phys_addr_with_space_nogpc()
3561 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr() argument
3629 return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); in get_phys_addr()
3645 ARMMMUFaultInfo fi = {}; in arm_cpu_get_phys_page_attrs_debug() local
3648 ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); in arm_cpu_get_phys_page_attrs_debug()