Lines Matching +full:low +full:- +full:profile
3 #include "qemu/error-report.h"
8 #include "cpu-features.h"
9 #include "migration/qemu-file-types.h"
17 return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) in vfp_needed()
35 * On incoming migration, if the cpu/vfp FPSCR field is non-zero we in vfp_fpcr_fpsr_needed()
37 * (The subsection will never be present with a non-zero FPSCR field, in vfp_fpcr_fpsr_needed()
45 CPUARMState *env = &cpu->env; in vfp_fpcr_fpsr_needed()
55 CPUARMState *env = &cpu->env; in get_fpscr()
69 CPUARMState *env = &cpu->env; in put_fpscr()
86 CPUARMState *env = &cpu->env; in get_fpcr()
97 CPUARMState *env = &cpu->env; in put_fpcr()
113 CPUARMState *env = &cpu->env; in get_fpsr()
124 CPUARMState *env = &cpu->env; in put_fpsr()
227 CPUARMState *env = &cpu->env; in iwmmxt_needed()
244 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
262 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2),
307 * It will be zeroed when ZA storage is re-enabled. in za_needed()
309 return FIELD_EX64(cpu->env.svcr, SVCR, ZA); in za_needed()
338 ARRAY_SIZE(((CPUARMState *)0)->za_state.zt0)),
346 CPUARMState *env = &cpu->env; in serror_needed()
348 return env->serror.pending != 0; in serror_needed()
370 .name = "cpu/irq-line-state",
385 return cpu->wfxt_timer; in wfxt_timer_needed()
389 .name = "cpu/wfxt-timer",
402 CPUARMState *env = &cpu->env; in m_needed()
408 .name = "cpu/m/faultmask-primask",
424 * just non-secure, we transfer both banks here rather than putting
425 * the secure banked version in the m-security subsection.
431 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK in csselr_vmstate_validate()
432 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; in csselr_vmstate_validate()
466 .name = "cpu/m/other-sp",
479 CPUARMState *env = &cpu->env; in m_v8m_needed()
564 CPUARMState *env = &cpu->env; in thumb2ee_needed()
584 CPUARMState *env = &cpu->env; in pmsav7_needed()
595 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; in pmsav7_rgnr_vmstate_validate()
618 CPUARMState *env = &cpu->env; in pmsav7_rnr_needed()
620 /* For R profile cores pmsav7.rnr is migrated via the cpreg in pmsav7_rnr_needed()
621 * "RGNR" definition in helper.h. For M profile we have to in pmsav7_rnr_needed()
628 .name = "cpu/pmsav7-rnr",
641 CPUARMState *env = &cpu->env; in pmsav8_needed()
650 CPUARMState *env = &cpu->env; in pmsav8r_needed()
695 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; in s_rnr_vmstate_validate()
702 return cpu->env.sau.rnr < cpu->sau_sregion; in sau_rnr_vmstate_validate()
708 CPUARMState *env = &cpu->env; in m_security_needed()
714 .name = "cpu/m-security",
749 /* AIRCR is not secure-only, but our implementation is R/O if the
761 CPUARMState *env = &cpu->env; in get_cpsr()
785 * an old QEMU which still stored the M profile FAULTMASK in get_cpsr()
786 * and PRIMASK in env->daif. For a new QEMU, the data is in get_cpsr()
790 env->v7m.faultmask[M_REG_NS] = 1; in get_cpsr()
793 env->v7m.primask[M_REG_NS] = 1; in get_cpsr()
797 /* Ignore the low bits, they are handled by vmstate_m. */ in get_cpsr()
802 env->aarch64 = ((val & PSTATE_nRW) == 0); in get_cpsr()
817 CPUARMState *env = &cpu->env; in put_cpsr()
821 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ in put_cpsr()
844 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; in get_power()
855 if (cpu->power_state == PSCI_ON || in put_power()
856 cpu->power_state == PSCI_OFF) { in put_power()
857 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; in put_power()
876 pmu_op_start(&cpu->env); in cpu_pre_save()
897 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; in cpu_pre_save()
898 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, in cpu_pre_save()
899 cpu->cpreg_array_len * sizeof(uint64_t)); in cpu_pre_save()
900 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, in cpu_pre_save()
901 cpu->cpreg_array_len * sizeof(uint64_t)); in cpu_pre_save()
911 pmu_op_finish(&cpu->env); in cpu_post_save()
920 CPUARMState *env = &cpu->env; in cpu_pre_load()
932 * future architecture change makes the reset value non-zero. in cpu_pre_load()
937 * Pre-initialize irq_line_state to a value that's never valid as in cpu_pre_load()
939 * irq-line-state subsection in the incoming migration state. in cpu_pre_load()
941 env->irq_line_state = UINT32_MAX; in cpu_pre_load()
953 CPUARMState *env = &cpu->env; in cpu_post_load()
958 * send the irq-line-state subsection. A QEMU without it did not in cpu_post_load()
960 * so for TCG the line state matches the bits set in cs->interrupt_request. in cpu_post_load()
961 * For KVM the line state is not stored in cs->interrupt_request in cpu_post_load()
965 if (env->irq_line_state == UINT32_MAX) { in cpu_post_load()
968 env->irq_line_state = cs->interrupt_request & in cpu_post_load()
977 * The indexes list remains untouched -- we only inspect the in cpu_post_load()
982 for (i = 0, v = 0; i < cpu->cpreg_array_len in cpu_post_load()
983 && v < cpu->cpreg_vmstate_array_len; i++) { in cpu_post_load()
984 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { in cpu_post_load()
988 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { in cpu_post_load()
990 return -1; in cpu_post_load()
993 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; in cpu_post_load()
999 return -1; in cpu_post_load()
1003 return -1; in cpu_post_load()
1012 if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { in cpu_post_load()
1013 return -1; in cpu_post_load()
1023 * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; in cpu_post_load()
1027 if (extract32(env->v7m.fpdscr[M_REG_NS], in cpu_post_load()
1029 extract32(env->v7m.fpdscr[M_REG_S], in cpu_post_load()
1031 return -1; in cpu_post_load()
1074 /* The length-check must come before the arrays to avoid