target/arm/internals.h

2  * QEMU ARM CPU -- internal functions and types
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
30 #include "tcg/tcg-gvec-desc.h"
32 #include "cpu-features.h"
46     return EX_TBFLAG_ANY(env->hflags, MMUIDX);  in arm_env_mmu_index()
51     /* Return true if this exception number represents a QEMU-internal  in excp_is_internal()
69  * We will use the back-compat value:
70  *  - for QEMU CPU types added before we standardized on 1GHz
71  *  - for versioned machine types with a version of 9.0 or earlier
91 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
124 /* Bit definitions for CPACR_EL1 (AArch64 only) */
138 /* Bit definitions for CPTR_EL2 (AArch64 only) */
149 /* Bit definitions for CPTR_EL3 (AArch64 only) */
179 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
295  * For AArch64, map a given EL to an index in the banked_spsr array.
297  * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
343  * This should be used as the index into env->banked_r14[], and
344  * bank_number() used for the index into env->banked_r13[] and
345  * env->banked_spsr[].
395     if (env->pstate & PSTATE_SP) {  in aarch64_save_sp()
396         env->sp_el[el] = env->xregs[31];  in aarch64_save_sp()
398         env->sp_el[0] = env->xregs[31];  in aarch64_save_sp()
404     if (env->pstate & PSTATE_SP) {  in aarch64_restore_sp()
405         env->xregs[31] = env->sp_el[el];  in aarch64_restore_sp()
407         env->xregs[31] = env->sp_el[0];  in aarch64_restore_sp()
417     if (!((imm ^ env->pstate) & PSTATE_SP)) {  in update_spsel()
421     env->pstate = deposit32(env->pstate, 0, 1, imm);  in update_spsel()
434  * Returns the implementation defined bit-width of physical addresses.
464     uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];  in extended_addresses_enabled()
478  * complete delete-and-reinstate of the QEMU watchpoint list and so is
479  * suitable for use after migration or on reset.
487  * complete delete-and-reinstate of the QEMU breakpoint list and so is
488  * suitable for use after migration or on reset.
529     env->exclusive_addr = -1;  in arm_clear_exclusive()
577  * @domain: Domain of the fault address (for non-LPAE CPUs only)
582  * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
583  * @s1ns: True if we faulted on a non-secure IPA while in secure state
602  * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
604  * we set up a whole FSR-format code including domain field and
611     switch (fi->type) {  in arm_fi_to_sfsc()
615         fsc = fi->level == 1 ? 0x3 : 0x6;  in arm_fi_to_sfsc()
621         fsc = fi->level == 1 ? 0xd : 0xf;  in arm_fi_to_sfsc()
624         fsc = fi->level == 1 ? 0x9 : 0xb;  in arm_fi_to_sfsc()
627         fsc = fi->level == 1 ? 0x5 : 0x7;  in arm_fi_to_sfsc()
630         fsc = 0x8 | (fi->ea << 12);  in arm_fi_to_sfsc()
633         fsc = fi->level == 1 ? 0xc : 0xe;  in arm_fi_to_sfsc()
634         fsc |= (fi->ea << 12);  in arm_fi_to_sfsc()
640         fsc = fi->level == 1 ? 0x40c : 0x40e;  in arm_fi_to_sfsc()
646         fsc = 0x406 | (fi->ea << 12);  in arm_fi_to_sfsc()
674          * short-format status code.  in arm_fi_to_sfsc()
679     fsc |= (fi->domain << 4);  in arm_fi_to_sfsc()
684  * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
692     switch (fi->type) {  in arm_fi_to_lfsc()
696         assert(fi->level >= -1 && fi->level <= 3);  in arm_fi_to_lfsc()
697         if (fi->level < 0) {  in arm_fi_to_lfsc()
700             fsc = fi->level;  in arm_fi_to_lfsc()
704         assert(fi->level >= 0 && fi->level <= 3);  in arm_fi_to_lfsc()
705         fsc = 0b001000 | fi->level;  in arm_fi_to_lfsc()
708         assert(fi->level >= 0 && fi->level <= 3);  in arm_fi_to_lfsc()
709         fsc = 0b001100 | fi->level;  in arm_fi_to_lfsc()
712         assert(fi->level >= -1 && fi->level <= 3);  in arm_fi_to_lfsc()
713         if (fi->level < 0) {  in arm_fi_to_lfsc()
716             fsc = 0b000100 | fi->level;  in arm_fi_to_lfsc()
720         fsc = 0x10 | (fi->ea << 12);  in arm_fi_to_lfsc()
723         assert(fi->level >= -1 && fi->level <= 3);  in arm_fi_to_lfsc()
724         if (fi->level < 0) {  in arm_fi_to_lfsc()
727             fsc = 0b010100 | fi->level;  in arm_fi_to_lfsc()
729         fsc |= fi->ea << 12;  in arm_fi_to_lfsc()
735         assert(fi->level >= -1 && fi->level <= 3);  in arm_fi_to_lfsc()
736         if (fi->level < 0) {  in arm_fi_to_lfsc()
739             fsc = 0b011100 | fi->level;  in arm_fi_to_lfsc()
746         fsc = 0x11 | (fi->ea << 12);  in arm_fi_to_lfsc()
767         assert(fi->level >= -1 && fi->level <= 3);  in arm_fi_to_lfsc()
768         if (fi->level < 0) {  in arm_fi_to_lfsc()
771             fsc = 0b100100 | fi->level;  in arm_fi_to_lfsc()
779          * long-format status code.  in arm_fi_to_lfsc()
826     /* AArch64 is always a-profile. */  in core_to_aa64_mmu_idx()
862     QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {  in arm_call_pre_el_change_hook()
863         hook->hook(cpu, hook->opaque);  in arm_call_pre_el_change_hook()
869     QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {  in arm_call_el_change_hook()
870         hook->hook(cpu, hook->opaque);  in arm_call_el_change_hook()
975     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];  in regime_sctlr()
980  * and the Non-Secure stage 2 translation regimes (and hence which are
992         return env->cp15.vtcr_el2;  in regime_tcr()
1003         uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK;  in regime_tcr()
1004         v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK;  in regime_tcr()
1007     return env->cp15.tcr_el[regime_el(env, mmu_idx)];  in regime_tcr()
1030  * Note that the ID register BRPS field is "number of bps - 1",
1035     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {  in arm_num_brps()
1036         return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;  in arm_num_brps()
1038         return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;  in arm_num_brps()
1044  * Note that the ID register WRPS field is "number of wps - 1",
1049     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {  in arm_num_wrps()
1050         return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;  in arm_num_wrps()
1052         return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;  in arm_num_wrps()
1058  * Note that the ID register CTX_CMPS field is "number of cmps - 1",
1063     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {  in arm_num_ctx_cmps()
1064         return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;  in arm_num_ctx_cmps()
1066         return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;  in arm_num_ctx_cmps()
1080      * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.  in v7m_using_psp()
1083         env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;  in v7m_using_psp()
1094         return env->v7m.psplim[env->v7m.secure];  in v7m_sp_limit()
1096         return env->v7m.msplim[env->v7m.secure];  in v7m_sp_limit()
1108     switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {  in v7m_cpacr_pass()
1140  * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
1142  * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
1149  * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
1151  * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
1158  * arm_cpu_update_vinmi: Update CPU_INTERRUPT_VINMI bit in cs->interrupt_request
1160  * Update the CPU_INTERRUPT_VINMI bit in cs->interrupt_request, following
1167  * arm_cpu_update_vfnmi: Update CPU_INTERRUPT_VFNMI bit in cs->interrupt_request
1169  * Update the CPU_INTERRUPT_VFNMI bit in cs->interrupt_request, following
1178  * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
1351  * aa64_va_parameters: Return parameters for an AArch64 virtual address
1373         && !(env->cp15.scr_el3 & SCR_ATA)) {  in allocation_tag_access_enabled()
1407      * Otherwise, attrs is the same as the MAIR_EL1 8-bit format
1410     unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
1500 FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12)  /* size - 1 */
1590  * for the tag to be present in the FAR_ELx register.  But for user-only
1614 /* Values for M-profile PSR.ECI for MVE insns */
1663     return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;  in pmu_num_counters()
1669   return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1);  in pmu_counter_mask()
1721     int bot_pac_bit = 64 - param.tsz;  in pauth_ptr_mask()
1722     int top_pac_bit = 64 - 8 * param.tbi;  in pauth_ptr_mask()
1724     return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);  in pauth_ptr_mask()
1733     return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;  in arm_mdcr_el2_eff()
1738     ((1 << (1 - 1)) | (1 << (2 - 1)) |                  \
1739      (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
1742  * Return true if it is possible to take a fine-grained-trap to EL2.
1751      * FGT traps only happen when EL2 is enabled and EL1 is AArch64;  in arm_fgt_active()
1758         (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));  in arm_fgt_active()
1765  * allows for different breakpoints per-core, the current GDB
1799 #define cur_hw_wps      (hw_watchpoints->len)
1800 #define cur_hw_bps      (hw_breakpoints->len)