Lines Matching refs:value
49 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in raw_write() argument
53 CPREG_FIELD64(env, ri) = value; in raw_write()
55 CPREG_FIELD32(env, ri) = value; in raw_write()
402 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in dacr_write() argument
406 raw_write(env, ri, value); in dacr_write()
410 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in fcse_write() argument
414 if (raw_read(env, ri) != value) { in fcse_write()
420 raw_write(env, ri, value); in fcse_write()
425 uint64_t value) in contextidr_write() argument
429 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) in contextidr_write()
438 raw_write(env, ri, value); in contextidr_write()
458 uint64_t value) in tlbiall_is_write() argument
466 uint64_t value) in tlbiasid_is_write() argument
474 uint64_t value) in tlbimva_is_write() argument
478 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); in tlbimva_is_write()
482 uint64_t value) in tlbimvaa_is_write() argument
486 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); in tlbimvaa_is_write()
500 uint64_t value) in tlbiall_write() argument
513 uint64_t value) in tlbimva_write() argument
518 value &= TARGET_PAGE_MASK; in tlbimva_write()
520 tlb_flush_page_all_cpus_synced(cs, value); in tlbimva_write()
522 tlb_flush_page(cs, value); in tlbimva_write()
527 uint64_t value) in tlbiasid_write() argument
540 uint64_t value) in tlbimvaa_write() argument
545 value &= TARGET_PAGE_MASK; in tlbimvaa_write()
547 tlb_flush_page_all_cpus_synced(cs, value); in tlbimvaa_write()
549 tlb_flush_page(cs, value); in tlbimvaa_write()
554 uint64_t value) in tlbiall_nsnh_write() argument
562 uint64_t value) in tlbiall_nsnh_is_write() argument
571 uint64_t value) in tlbiall_hyp_write() argument
579 uint64_t value) in tlbiall_hyp_is_write() argument
587 uint64_t value) in tlbimva_hyp_write() argument
590 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); in tlbimva_hyp_write()
596 uint64_t value) in tlbimva_hyp_is_write() argument
599 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); in tlbimva_hyp_is_write()
606 uint64_t value) in tlbiipas2_hyp_write() argument
609 uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; in tlbiipas2_hyp_write()
615 uint64_t value) in tlbiipas2is_hyp_write() argument
618 uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; in tlbiipas2is_hyp_write()
755 uint64_t value) in cpacr_write() argument
775 value |= R_CPACR_ASEDIS_MASK; in cpacr_write()
784 value |= R_CPACR_D32DIS_MASK; in cpacr_write()
787 value &= mask; in cpacr_write()
797 value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); in cpacr_write()
800 env->cp15.cpacr_el1 = value; in cpacr_write()
809 uint64_t value = env->cp15.cpacr_el1; in cpacr_read() local
813 value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); in cpacr_read()
815 return value; in cpacr_read()
1482 uint64_t value) in pmcr_write() argument
1486 if (value & PMCRC) { in pmcr_write()
1491 if (value & PMCRP) { in pmcr_write()
1499 env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); in pmcr_write()
1521 uint64_t value) in pmswinc_write() argument
1528 if ((value & (1 << i)) && /* counter's bit is set */ in pmswinc_write()
1566 uint64_t value) in pmselr_write() argument
1574 env->cp15.c9_pmselr = value & 0x1f; in pmselr_write()
1578 uint64_t value) in pmccntr_write() argument
1581 env->cp15.c15_ccnt = value; in pmccntr_write()
1586 uint64_t value) in pmccntr_write32() argument
1590 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); in pmccntr_write32()
1594 uint64_t value) in pmccfiltr_write() argument
1597 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; in pmccfiltr_write()
1602 uint64_t value) in pmccfiltr_write_a32() argument
1607 (value & PMCCFILTR); in pmccfiltr_write_a32()
1618 uint64_t value) in pmcntenset_write() argument
1621 value &= pmu_counter_mask(env); in pmcntenset_write()
1622 env->cp15.c9_pmcnten |= value; in pmcntenset_write()
1627 uint64_t value) in pmcntenclr_write() argument
1630 value &= pmu_counter_mask(env); in pmcntenclr_write()
1631 env->cp15.c9_pmcnten &= ~value; in pmcntenclr_write()
1636 uint64_t value) in pmovsr_write() argument
1638 value &= pmu_counter_mask(env); in pmovsr_write()
1639 env->cp15.c9_pmovsr &= ~value; in pmovsr_write()
1644 uint64_t value) in pmovsset_write() argument
1646 value &= pmu_counter_mask(env); in pmovsset_write()
1647 env->cp15.c9_pmovsr |= value; in pmovsset_write()
1652 uint64_t value, const uint8_t counter) in pmevtyper_write() argument
1655 pmccfiltr_write(env, ri, value); in pmevtyper_write()
1667 uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; in pmevtyper_write()
1677 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; in pmevtyper_write()
1704 uint64_t value) in pmevtyper_writefn() argument
1707 pmevtyper_write(env, ri, value, counter); in pmevtyper_writefn()
1711 uint64_t value) in pmevtyper_rawwrite() argument
1714 env->cp15.c14_pmevtyper[counter] = value; in pmevtyper_rawwrite()
1725 uint16_t event = value & PMXEVTYPER_EVTCOUNT; in pmevtyper_rawwrite()
1740 uint64_t value) in pmxevtyper_write() argument
1742 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevtyper_write()
1751 uint64_t value, uint8_t counter) in pmevcntr_write() argument
1755 value &= MAKE_64BIT_MASK(0, 32); in pmevcntr_write()
1759 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_write()
1791 uint64_t value) in pmevcntr_writefn() argument
1794 pmevcntr_write(env, ri, value, counter); in pmevcntr_writefn()
1804 uint64_t value) in pmevcntr_rawwrite() argument
1808 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_rawwrite()
1809 pmevcntr_write(env, ri, value, counter); in pmevcntr_rawwrite()
1820 uint64_t value) in pmxevcntr_write() argument
1822 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevcntr_write()
1831 uint64_t value) in pmuserenr_write() argument
1834 env->cp15.c9_pmuserenr = value & 0xf; in pmuserenr_write()
1836 env->cp15.c9_pmuserenr = value & 1; in pmuserenr_write()
1841 uint64_t value) in pmintenset_write() argument
1844 value &= pmu_counter_mask(env); in pmintenset_write()
1845 env->cp15.c9_pminten |= value; in pmintenset_write()
1850 uint64_t value) in pmintenclr_write() argument
1852 value &= pmu_counter_mask(env); in pmintenclr_write()
1853 env->cp15.c9_pminten &= ~value; in pmintenclr_write()
1858 uint64_t value) in vbar_write() argument
1867 raw_write(env, ri, value & ~0x1FULL); in vbar_write()
1870 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in scr_write() argument
1883 value |= SCR_FW | SCR_AW; /* RES1 */ in scr_write()
1888 value |= SCR_RW; /* RAO/WI */ in scr_write()
1903 value |= SCR_NS; in scr_write()
1953 value &= valid_mask; in scr_write()
1954 changed = env->cp15.scr_el3 ^ value; in scr_write()
1955 env->cp15.scr_el3 = value; in scr_write()
2008 uint64_t value) in csselr_write() argument
2010 raw_write(env, ri, value & 0xf); in csselr_write()
2402 uint64_t value) in teecr_write() argument
2404 value &= 1; in teecr_write()
2405 env->teecr = value; in teecr_write()
2832 uint64_t value) in gt_cval_write() argument
2834 trace_arm_gt_cval_write(timeridx, value); in gt_cval_write()
2835 env->cp15.c14_timer[timeridx].cval = value; in gt_cval_write()
2860 uint64_t value) in gt_tval_write() argument
2874 trace_arm_gt_tval_write(timeridx, value); in gt_tval_write()
2876 sextract64(value, 0, 32); in gt_tval_write()
2882 uint64_t value) in gt_ctl_write() argument
2887 trace_arm_gt_ctl_write(timeridx, value); in gt_ctl_write()
2888 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); in gt_ctl_write()
2889 if ((oldval ^ value) & 1) { in gt_ctl_write()
2892 } else if ((oldval ^ value) & 2) { in gt_ctl_write()
2908 uint64_t value) in gt_phys_cval_write() argument
2910 gt_cval_write(env, ri, GTIMER_PHYS, value); in gt_phys_cval_write()
2919 uint64_t value) in gt_phys_tval_write() argument
2921 gt_tval_write(env, ri, GTIMER_PHYS, value); in gt_phys_tval_write()
2925 uint64_t value) in gt_phys_ctl_write() argument
2927 gt_ctl_write(env, ri, GTIMER_PHYS, value); in gt_phys_ctl_write()
2962 uint64_t value) in gt_phys_redir_cval_write() argument
2965 gt_cval_write(env, ri, timeridx, value); in gt_phys_redir_cval_write()
2976 uint64_t value) in gt_phys_redir_tval_write() argument
2979 gt_tval_write(env, ri, timeridx, value); in gt_phys_redir_tval_write()
2990 uint64_t value) in gt_phys_redir_ctl_write() argument
2993 gt_ctl_write(env, ri, timeridx, value); in gt_phys_redir_ctl_write()
3002 uint64_t value) in gt_virt_cval_write() argument
3004 gt_cval_write(env, ri, GTIMER_VIRT, value); in gt_virt_cval_write()
3013 uint64_t value) in gt_virt_tval_write() argument
3015 gt_tval_write(env, ri, GTIMER_VIRT, value); in gt_virt_tval_write()
3019 uint64_t value) in gt_virt_ctl_write() argument
3021 gt_ctl_write(env, ri, GTIMER_VIRT, value); in gt_virt_ctl_write()
3025 uint64_t value) in gt_cnthctl_write() argument
3056 value &= valid_mask; in gt_cnthctl_write()
3058 raw_write(env, ri, value); in gt_cnthctl_write()
3060 if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { in gt_cnthctl_write()
3062 } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { in gt_cnthctl_write()
3068 uint64_t value) in gt_cntvoff_write() argument
3072 trace_arm_gt_cntvoff_write(value); in gt_cntvoff_write()
3073 raw_write(env, ri, value); in gt_cntvoff_write()
3085 uint64_t value) in gt_virt_redir_cval_write() argument
3088 gt_cval_write(env, ri, timeridx, value); in gt_virt_redir_cval_write()
3099 uint64_t value) in gt_virt_redir_tval_write() argument
3102 gt_tval_write(env, ri, timeridx, value); in gt_virt_redir_tval_write()
3113 uint64_t value) in gt_virt_redir_ctl_write() argument
3116 gt_ctl_write(env, ri, timeridx, value); in gt_virt_redir_ctl_write()
3125 uint64_t value) in gt_hyp_cval_write() argument
3127 gt_cval_write(env, ri, GTIMER_HYP, value); in gt_hyp_cval_write()
3136 uint64_t value) in gt_hyp_tval_write() argument
3138 gt_tval_write(env, ri, GTIMER_HYP, value); in gt_hyp_tval_write()
3142 uint64_t value) in gt_hyp_ctl_write() argument
3144 gt_ctl_write(env, ri, GTIMER_HYP, value); in gt_hyp_ctl_write()
3153 uint64_t value) in gt_sec_cval_write() argument
3155 gt_cval_write(env, ri, GTIMER_SEC, value); in gt_sec_cval_write()
3164 uint64_t value) in gt_sec_tval_write() argument
3166 gt_tval_write(env, ri, GTIMER_SEC, value); in gt_sec_tval_write()
3170 uint64_t value) in gt_sec_ctl_write() argument
3172 gt_ctl_write(env, ri, GTIMER_SEC, value); in gt_sec_ctl_write()
3181 uint64_t value) in gt_hv_cval_write() argument
3183 gt_cval_write(env, ri, GTIMER_HYPVIRT, value); in gt_hv_cval_write()
3192 uint64_t value) in gt_hv_tval_write() argument
3194 gt_tval_write(env, ri, GTIMER_HYPVIRT, value); in gt_hv_tval_write()
3198 uint64_t value) in gt_hv_ctl_write() argument
3200 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); in gt_hv_ctl_write()
3476 uint64_t value) in gt_cntpoff_write() argument
3480 trace_arm_gt_cntpoff_write(value); in gt_cntpoff_write()
3481 raw_write(env, ri, value); in gt_cntpoff_write()
3540 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in par_write() argument
3543 raw_write(env, ri, value); in par_write()
3545 raw_write(env, ri, value & 0xfffff6ff); in par_write()
3547 raw_write(env, ri, value & 0xfffff1ff); in par_write()
3591 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, in do_ats_write() argument
3605 ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, in do_ats_write()
3678 env->exception.vaddress = value; in do_ats_write()
3764 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in ats_write() argument
3823 par64 = do_ats_write(env, value, access_type, mmu_idx, ss); in ats_write()
3833 uint64_t value) in ats1h_write() argument
3840 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, in ats1h_write()
3886 uint64_t value) in ats_write64() argument
3932 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss); in ats_write64()
3971 uint64_t value) in pmsav5_data_ap_write() argument
3973 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); in pmsav5_data_ap_write()
3982 uint64_t value) in pmsav5_insn_ap_write() argument
3984 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); in pmsav5_insn_ap_write()
4005 uint64_t value) in pmsav7_write() argument
4016 *u32p = value; in pmsav7_write()
4020 uint64_t value) in pmsav7_rgnr_write() argument
4025 if (value >= nrgs) { in pmsav7_rgnr_write()
4028 " > %" PRIu32 "\n", (uint32_t)value, nrgs); in pmsav7_rgnr_write()
4032 raw_write(env, ri, value); in pmsav7_rgnr_write()
4036 uint64_t value) in prbar_write() argument
4041 env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prbar_write()
4050 uint64_t value) in prlar_write() argument
4055 env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prlar_write()
4064 uint64_t value) in prselr_write() argument
4072 if (value >= cpu->pmsav7_dregion) { in prselr_write()
4076 env->pmsav7.rnr[M_REG_NS] = value; in prselr_write()
4080 uint64_t value) in hprbar_write() argument
4085 env->pmsav8.hprbar[env->pmsav8.hprselr] = value; in hprbar_write()
4094 uint64_t value) in hprlar_write() argument
4099 env->pmsav8.hprlar[env->pmsav8.hprselr] = value; in hprlar_write()
4108 uint64_t value) in hprenr_write() argument
4116 value &= MAKE_64BIT_MASK(0, rmax); in hprenr_write()
4122 bit = extract32(value, n, 1); in hprenr_write()
4144 uint64_t value) in hprselr_write() argument
4152 if (value >= cpu->pmsav8r_hdregion) { in hprselr_write()
4156 env->pmsav8.hprselr = value; in hprselr_write()
4160 uint64_t value) in pmsav8r_regn_write() argument
4173 env->pmsav8.hprlar[index] = value; in pmsav8r_regn_write()
4175 env->pmsav8.hprbar[index] = value; in pmsav8r_regn_write()
4182 env->pmsav8.rlar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4184 env->pmsav8.rbar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4330 uint64_t value) in vmsa_ttbcr_write() argument
4335 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { in vmsa_ttbcr_write()
4340 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); in vmsa_ttbcr_write()
4347 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; in vmsa_ttbcr_write()
4349 value &= TTBCR_N; in vmsa_ttbcr_write()
4360 raw_write(env, ri, value); in vmsa_ttbcr_write()
4364 uint64_t value) in vmsa_tcr_el12_write() argument
4370 raw_write(env, ri, value); in vmsa_tcr_el12_write()
4374 uint64_t value) in vmsa_ttbr_write() argument
4378 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { in vmsa_ttbr_write()
4382 raw_write(env, ri, value); in vmsa_ttbr_write()
4386 uint64_t value) in vmsa_tcr_ttbr_el2_write() argument
4394 if (extract64(raw_read(env, ri) ^ value, 48, 16) && in vmsa_tcr_ttbr_el2_write()
4401 raw_write(env, ri, value); in vmsa_tcr_ttbr_el2_write()
4405 uint64_t value) in vttbr_write() argument
4414 if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { in vttbr_write()
4417 raw_write(env, ri, value); in vttbr_write()
4497 uint64_t value) in omap_ticonfig_write() argument
4499 env->cp15.c15_ticonfig = value & 0xe7; in omap_ticonfig_write()
4501 env->cp15.c0_cpuid = (value & (1 << 5)) ? in omap_ticonfig_write()
4506 uint64_t value) in omap_threadid_write() argument
4508 env->cp15.c15_threadid = value & 0xffff; in omap_threadid_write()
4512 uint64_t value) in omap_wfi_write() argument
4519 uint64_t value) in omap_cachemaint_write() argument
4570 uint64_t value) in xscale_cpar_write() argument
4572 env->cp15.c15_cpar = value & 0x3fff; in xscale_cpar_write()
4739 uint64_t value) in aa64_fpcr_write() argument
4741 vfp_set_fpcr(env, value); in aa64_fpcr_write()
4750 uint64_t value) in aa64_fpsr_write() argument
4752 vfp_set_fpsr(env, value); in aa64_fpsr_write()
4765 uint64_t value) in aa64_daif_write() argument
4767 env->daif = value & PSTATE_DAIF; in aa64_daif_write()
4776 uint64_t value) in aa64_pan_write() argument
4778 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); in aa64_pan_write()
4794 uint64_t value) in aa64_uao_write() argument
4796 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); in aa64_uao_write()
4812 uint64_t value) in aa64_dit_write() argument
4814 env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); in aa64_dit_write()
4830 uint64_t value) in aa64_ssbs_write() argument
4832 env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); in aa64_ssbs_write()
4979 uint64_t value) in tlbi_aa64_vmalle1is_write() argument
4988 uint64_t value) in tlbi_aa64_vmalle1_write() argument
5009 uint64_t value) in tlbi_aa64_alle1_write() argument
5018 uint64_t value) in tlbi_aa64_alle2_write() argument
5027 uint64_t value) in tlbi_aa64_alle3_write() argument
5036 uint64_t value) in tlbi_aa64_alle1is_write() argument
5045 uint64_t value) in tlbi_aa64_alle2is_write() argument
5054 uint64_t value) in tlbi_aa64_alle3is_write() argument
5062 uint64_t value) in tlbi_aa64_vae2_write() argument
5071 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_vae2_write()
5078 uint64_t value) in tlbi_aa64_vae3_write() argument
5087 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_vae3_write()
5093 uint64_t value) in tlbi_aa64_vae1is_write() argument
5097 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_vae1is_write()
5104 uint64_t value) in tlbi_aa64_vae1_write() argument
5114 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_vae1_write()
5125 uint64_t value) in tlbi_aa64_vae2is_write() argument
5129 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_vae2is_write()
5136 uint64_t value) in tlbi_aa64_vae3is_write() argument
5139 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_vae3is_write()
5146 static int ipas2e1_tlbmask(CPUARMState *env, int64_t value) in ipas2e1_tlbmask() argument
5152 return (value >= 0 in ipas2e1_tlbmask()
5160 uint64_t value) in tlbi_aa64_ipas2e1_write() argument
5163 int mask = ipas2e1_tlbmask(env, value); in tlbi_aa64_ipas2e1_write()
5164 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_ipas2e1_write()
5174 uint64_t value) in tlbi_aa64_ipas2e1is_write() argument
5177 int mask = ipas2e1_tlbmask(env, value); in tlbi_aa64_ipas2e1is_write()
5178 uint64_t pageaddr = sextract64(value << 12, 0, 56); in tlbi_aa64_ipas2e1is_write()
5208 uint64_t value) in tlbi_aa64_get_range() argument
5212 uint64_t select = sextract64(value, 36, 1); in tlbi_aa64_get_range()
5217 page_size_granule = extract64(value, 46, 2); in tlbi_aa64_get_range()
5228 num = extract64(value, 39, 5); in tlbi_aa64_get_range()
5229 scale = extract64(value, 44, 2); in tlbi_aa64_get_range()
5235 ret.base = sextract64(value, 0, 37); in tlbi_aa64_get_range()
5237 ret.base = extract64(value, 0, 37); in tlbi_aa64_get_range()
5252 static void do_rvae_write(CPUARMState *env, uint64_t value, in do_rvae_write() argument
5259 range = tlbi_aa64_get_range(env, one_idx, value); in do_rvae_write()
5276 uint64_t value) in tlbi_aa64_rvae1_write() argument
5285 do_rvae_write(env, value, vae1_tlbmask(env), in tlbi_aa64_rvae1_write()
5291 uint64_t value) in tlbi_aa64_rvae1is_write() argument
5301 do_rvae_write(env, value, vae1_tlbmask(env), true); in tlbi_aa64_rvae1is_write()
5306 uint64_t value) in tlbi_aa64_rvae2_write() argument
5315 do_rvae_write(env, value, vae2_tlbmask(env), in tlbi_aa64_rvae2_write()
5323 uint64_t value) in tlbi_aa64_rvae2is_write() argument
5332 do_rvae_write(env, value, vae2_tlbmask(env), true); in tlbi_aa64_rvae2is_write()
5338 uint64_t value) in tlbi_aa64_rvae3_write() argument
5347 do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); in tlbi_aa64_rvae3_write()
5352 uint64_t value) in tlbi_aa64_rvae3is_write() argument
5361 do_rvae_write(env, value, ARMMMUIdxBit_E3, true); in tlbi_aa64_rvae3is_write()
5365 uint64_t value) in tlbi_aa64_ripas2e1_write() argument
5367 do_rvae_write(env, value, ipas2e1_tlbmask(env, value), in tlbi_aa64_ripas2e1_write()
5373 uint64_t value) in tlbi_aa64_ripas2e1is_write() argument
5375 do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true); in tlbi_aa64_ripas2e1is_write()
5443 uint64_t value) in sctlr_write() argument
5449 value &= ~SCTLR_M; in sctlr_write()
5456 value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); in sctlr_write()
5458 value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | in sctlr_write()
5463 if (raw_read(env, ri) == value) { in sctlr_write()
5471 raw_write(env, ri, value); in sctlr_write()
5488 uint64_t value) in mdcr_el3_write() argument
5495 bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; in mdcr_el3_write()
5500 env->cp15.mdcr_el3 = value; in mdcr_el3_write()
5507 uint64_t value) in sdcr_write() argument
5510 mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); in sdcr_write()
5514 uint64_t value) in mdcr_el2_write() argument
5521 bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; in mdcr_el2_write()
5526 env->cp15.mdcr_el2 = value; in mdcr_el2_write()
5556 uint64_t value) in ic_ivau_write() argument
5564 start_address = value & ~icache_line_mask; in ic_ivau_write()
5565 end_address = value | icache_line_mask; in ic_ivau_write()
5973 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) in do_hcr_write() argument
6037 value &= valid_mask; in do_hcr_write()
6048 if ((env->cp15.hcr_el2 ^ value) & in do_hcr_write()
6052 env->cp15.hcr_el2 = value; in do_hcr_write()
6075 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in hcr_write() argument
6077 do_hcr_write(env, value, 0); in hcr_write()
6081 uint64_t value) in hcr_writehigh() argument
6084 value = deposit64(env->cp15.hcr_el2, 32, 32, value); in hcr_writehigh()
6085 do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); in hcr_writehigh()
6089 uint64_t value) in hcr_writelow() argument
6092 value = deposit64(env->cp15.hcr_el2, 0, 32, value); in hcr_writelow()
6093 do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); in hcr_writelow()
6203 uint64_t value) in hcrx_write() argument
6219 env->cp15.hcrx_el2 = value & valid_mask; in hcrx_write()
6288 uint64_t value) in cptr_el2_write() argument
6297 value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); in cptr_el2_write()
6299 env->cp15.cptr_el[2] = value; in cptr_el2_write()
6308 uint64_t value = env->cp15.cptr_el[2]; in cptr_el2_read() local
6312 value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; in cptr_el2_read()
6314 return value; in cptr_el2_read()
6783 uint64_t value) in el2_e2h_write() argument
6797 writefn(env, ri, value); in el2_e2h_write()
6807 uint64_t value) in el2_e2h_e12_write() argument
6810 return ri->orig_writefn(env, ri->opaque, value); in el2_e2h_e12_write()
7256 uint64_t value) in zcr_write() argument
7264 raw_write(env, ri, value & 0xf); in zcr_write()
7379 uint64_t value) in svcr_write() argument
7381 aarch64_set_svcr(env, value, -1); in svcr_write()
7385 uint64_t value) in smcr_write() argument
7392 value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; in smcr_write()
7393 raw_write(env, ri, value); in smcr_write()
7461 uint64_t value) in tlbi_aa64_paall_write() argument
7469 uint64_t value) in gpccr_write() argument
7476 env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); in gpccr_write()
7486 uint64_t value) in tlbi_aa64_paallos_write() argument
7538 uint64_t value) in aa64_allint_write() argument
7540 env->pstate = (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLINT); in aa64_allint_write()
8074 uint64_t value) in dccvap_writefn() argument
8080 uint64_t vaddr_in = (uint64_t) value; in dccvap_writefn()
8435 uint64_t value) in vncr_write() argument
8444 env->cp15.vncr_el2 = value & ~0xfffULL; in vncr_write()
10427 uint64_t value) in arm_cp_write_ignore() argument