Lines Matching +full:ipa +full:- +full:clock +full:- +full:enabled +full:- +full:valid
6 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
24 #include "sysemu/cpu-timers.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
41 assert(ri->fieldoffset); in raw_read()
51 assert(ri->fieldoffset); in raw_write()
61 return (char *)env + ri->fieldoffset; in raw_ptr()
67 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg()
68 return ri->resetvalue; in read_raw_cp_reg()
69 } else if (ri->raw_readfn) { in read_raw_cp_reg()
70 return ri->raw_readfn(env, ri); in read_raw_cp_reg()
71 } else if (ri->readfn) { in read_raw_cp_reg()
72 return ri->readfn(env, ri); in read_raw_cp_reg()
83 * Note that constant registers are treated as write-ignored; the in write_raw_cp_reg()
87 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg()
89 } else if (ri->raw_writefn) { in write_raw_cp_reg()
90 ri->raw_writefn(env, ri, v); in write_raw_cp_reg()
91 } else if (ri->writefn) { in write_raw_cp_reg()
92 ri->writefn(env, ri, v); in write_raw_cp_reg()
112 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid()
113 ri->fieldoffset || in raw_accessors_invalid()
114 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { in raw_accessors_invalid()
122 /* Write the coprocessor state from cpu->env to the (index,value) list. */ in write_cpustate_to_list()
126 for (i = 0; i < cpu->cpreg_array_len; i++) { in write_cpustate_to_list()
127 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); in write_cpustate_to_list()
131 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in write_cpustate_to_list()
136 if (ri->type & ARM_CP_NO_RAW) { in write_cpustate_to_list()
140 newval = read_raw_cp_reg(&cpu->env, ri); in write_cpustate_to_list()
143 * Only sync if the previous list->cpustate sync succeeded. in write_cpustate_to_list()
148 uint64_t oldval = cpu->cpreg_values[i]; in write_cpustate_to_list()
154 write_raw_cp_reg(&cpu->env, ri, oldval); in write_cpustate_to_list()
155 if (read_raw_cp_reg(&cpu->env, ri) != oldval) { in write_cpustate_to_list()
159 write_raw_cp_reg(&cpu->env, ri, newval); in write_cpustate_to_list()
161 cpu->cpreg_values[i] = newval; in write_cpustate_to_list()
171 for (i = 0; i < cpu->cpreg_array_len; i++) { in write_list_to_cpustate()
172 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); in write_list_to_cpustate()
173 uint64_t v = cpu->cpreg_values[i]; in write_list_to_cpustate()
176 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in write_list_to_cpustate()
181 if (ri->type & ARM_CP_NO_RAW) { in write_list_to_cpustate()
186 * (to catch read-only registers and partially read-only in write_list_to_cpustate()
189 write_raw_cp_reg(&cpu->env, ri, v); in write_list_to_cpustate()
190 if (read_raw_cp_reg(&cpu->env, ri) != v) { in write_list_to_cpustate()
201 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in add_cpreg_to_list()
203 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { in add_cpreg_to_list()
204 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); in add_cpreg_to_list()
206 cpu->cpreg_array_len++; in add_cpreg_to_list()
215 ri = g_hash_table_lookup(cpu->cp_regs, key); in count_cpreg()
217 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { in count_cpreg()
218 cpu->cpreg_array_len++; in count_cpreg()
231 return -1; in cpreg_key_compare()
245 keys = g_hash_table_get_keys(cpu->cp_regs); in init_cpreg_list()
248 cpu->cpreg_array_len = 0; in init_cpreg_list()
252 arraylen = cpu->cpreg_array_len; in init_cpreg_list()
253 cpu->cpreg_indexes = g_new(uint64_t, arraylen); in init_cpreg_list()
254 cpu->cpreg_values = g_new(uint64_t, arraylen); in init_cpreg_list()
255 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); in init_cpreg_list()
256 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); in init_cpreg_list()
257 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; in init_cpreg_list()
258 cpu->cpreg_array_len = 0; in init_cpreg_list()
262 assert(cpu->cpreg_array_len == arraylen); in init_cpreg_list()
273 return env->pstate & PSTATE_PAN; in arm_pan_enabled()
275 return env->uncached_cpsr & CPSR_PAN; in arm_pan_enabled()
294 * Some secure-only AArch32 registers trap to EL3 if used from
295 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
307 if (env->cp15.scr_el3 & SCR_EEL2) { in access_trap_aa32s_el1()
329 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in access_tpm()
493 * Non-IS variants of TLB operations are upgraded to
628 * Define the secure and non-secure FCSE identifier CP registers
631 * v8 EL1 version of the register so the non-secure instance stands alone.
644 * Define the secure and non-secure context identifier CP registers
647 * non-secure case, the 32-bit register will have reset and migration
648 * disabled during registration as it is handled by the 64-bit instance.
698 * Not all pre-v6 cores implemented this WFI, so this is slightly
699 * over-broad.
707 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
728 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
737 * the unified TLB ops but also the dside/iside/inner-shareable variants.
783 * registers (D0-D31). in cpacr_write()
786 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ in cpacr_write()
794 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 in cpacr_write()
798 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cpacr_write()
800 value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); in cpacr_write()
803 env->cp15.cpacr_el1 = value; in cpacr_write()
809 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 in cpacr_read()
812 uint64_t value = env->cp15.cpacr_el1; in cpacr_read()
815 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cpacr_read()
837 FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { in cpacr_access()
841 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { in cpacr_access()
854 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { in cptr_access()
867 * We need to break the TB after ISB to execute self-modifying code
930 return -1; in swinc_ns_per()
993 return -1; in zero_event_ns_per()
1052 * Empty supported_event_map and cpu->pmceid[01] before adding supported in pmu_init()
1058 cpu->pmceid0 = 0; in pmu_init()
1059 cpu->pmceid1 = 0; in pmu_init()
1063 assert(cnt->number <= MAX_EVENT_ID); in pmu_init()
1065 assert(cnt->number <= 0x3f); in pmu_init()
1067 if (cnt->supported(&cpu->env)) { in pmu_init()
1068 supported_event_map[cnt->number] = i; in pmu_init()
1069 uint64_t event_mask = 1ULL << (cnt->number & 0x1f); in pmu_init()
1070 if (cnt->number & 0x20) { in pmu_init()
1071 cpu->pmceid1 |= event_mask; in pmu_init()
1073 cpu->pmceid0 |= event_mask; in pmu_init()
1101 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { in pmreg_access()
1107 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in pmreg_access()
1121 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 in pmreg_access_xevcntr()
1136 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 in pmreg_access_swinc()
1151 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { in pmreg_access_selr()
1165 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 in pmreg_access_ccntr()
1190 bool enabled, prohibited = false, filtered; in pmu_counter_enabled() local
1197 * We might be called for M-profile cores where MDCR_EL2 doesn't in pmu_counter_enabled()
1198 * exist and arm_mdcr_el2_eff() will assert, so this early-exit check in pmu_counter_enabled()
1210 e = env->cp15.c9_pmcr & PMCRE; in pmu_counter_enabled()
1214 enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
1221 prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
1230 prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; in pmu_counter_enabled()
1233 prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); in pmu_counter_enabled()
1242 filter = env->cp15.pmccfiltr_el0; in pmu_counter_enabled()
1244 filter = env->cp15.c14_pmevtyper[counter]; in pmu_counter_enabled()
1276 return enabled && !prohibited && !filtered; in pmu_counter_enabled()
1282 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_update_irq()
1283 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq()
1289 * Return true if the clock divider is enabled and the cycle counter in pmccntr_clockdiv_enabled()
1290 * is supposed to tick only once every 64 clock cycles. This is in pmccntr_clockdiv_enabled()
1292 * (64-bit) cycle counter PMCR.D has no effect. in pmccntr_clockdiv_enabled()
1294 return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; in pmccntr_clockdiv_enabled()
1313 bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; in pmevcntr_is_64_bit()
1314 int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; in pmevcntr_is_64_bit()
1320 return env->cp15.c9_pmcr & PMCRLP; in pmevcntr_is_64_bit()
1324 * Ensure c15_ccnt is the guest-visible count so that operations such as
1326 * etc. can be done logically. This is essentially a no-op if the counter is
1327 * not enabled at the time of the call.
1339 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; in pmccntr_op_start()
1341 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ in pmccntr_op_start()
1343 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { in pmccntr_op_start()
1344 env->cp15.c9_pmovsr |= (1ULL << 31); in pmccntr_op_start()
1348 env->cp15.c15_ccnt = new_pmccntr; in pmccntr_op_start()
1350 env->cp15.c15_ccnt_delta = cycles; in pmccntr_op_start()
1354 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1355 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1363 uint64_t remaining_cycles = -env->cp15.c15_ccnt; in pmccntr_op_finish()
1364 if (!(env->cp15.c9_pmcr & PMCRLC)) { in pmccntr_op_finish()
1375 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); in pmccntr_op_finish()
1380 uint64_t prev_cycles = env->cp15.c15_ccnt_delta; in pmccntr_op_finish()
1384 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; in pmccntr_op_finish()
1391 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_start()
1399 uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; in pmevcntr_op_start()
1403 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { in pmevcntr_op_start()
1404 env->cp15.c9_pmovsr |= (1 << counter); in pmevcntr_op_start()
1407 env->cp15.c14_pmevcntr[counter] = new_pmevcntr; in pmevcntr_op_start()
1409 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevcntr_op_start()
1416 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_finish()
1418 uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); in pmevcntr_op_finish()
1432 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); in pmevcntr_op_finish()
1437 env->cp15.c14_pmevcntr_delta[counter] -= in pmevcntr_op_finish()
1438 env->cp15.c14_pmevcntr[counter]; in pmevcntr_op_finish()
1462 pmu_op_start(&cpu->env); in pmu_pre_el_change()
1467 pmu_op_finish(&cpu->env); in pmu_post_el_change()
1477 * has the effect of setting the cpu->pmu_timer to the next earliest time a in arm_pmu_timer_cb()
1480 pmu_op_start(&cpu->env); in arm_pmu_timer_cb()
1481 pmu_op_finish(&cpu->env); in arm_pmu_timer_cb()
1491 env->cp15.c15_ccnt = 0; in pmcr_write()
1497 env->cp15.c14_pmevcntr[i] = 0; in pmcr_write()
1501 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in pmcr_write()
1502 env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); in pmcr_write()
1509 uint64_t pmcr = env->cp15.c9_pmcr; in pmcr_read()
1512 * If EL2 is implemented and enabled for the current security state, reads in pmcr_read()
1517 pmcr |= (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; in pmcr_read()
1532 /* counter is enabled and not filtered */ in pmswinc_write()
1535 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { in pmswinc_write()
1542 new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; in pmswinc_write()
1547 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { in pmswinc_write()
1548 env->cp15.c9_pmovsr |= (1 << i); in pmswinc_write()
1552 env->cp15.c14_pmevcntr[i] = new_pmswinc; in pmswinc_write()
1563 ret = env->cp15.c15_ccnt; in pmccntr_read()
1577 env->cp15.c9_pmselr = value & 0x1f; in pmselr_write()
1584 env->cp15.c15_ccnt = value; in pmccntr_write()
1600 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; in pmccfiltr_write()
1609 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | in pmccfiltr_write_a32()
1617 return env->cp15.pmccfiltr_el0 & PMCCFILTR; in pmccfiltr_read_a32()
1625 env->cp15.c9_pmcnten |= value; in pmcntenset_write()
1634 env->cp15.c9_pmcnten &= ~value; in pmcntenclr_write()
1642 env->cp15.c9_pmovsr &= ~value; in pmovsr_write()
1650 env->cp15.c9_pmovsr |= value; in pmovsset_write()
1668 uint16_t old_event = env->cp15.c14_pmevtyper[counter] & in pmevtyper_write()
1677 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevtyper_write()
1680 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; in pmevtyper_write()
1694 return env->cp15.pmccfiltr_el0; in pmevtyper_read()
1696 return env->cp15.c14_pmevtyper[counter]; in pmevtyper_read()
1709 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_writefn()
1716 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_rawwrite()
1717 env->cp15.c14_pmevtyper[counter] = value; in pmevtyper_rawwrite()
1731 env->cp15.c14_pmevcntr_delta[counter] = in pmevtyper_rawwrite()
1738 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_readfn()
1745 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevtyper_write()
1750 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevtyper_read()
1762 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_write()
1777 ret = env->cp15.c14_pmevcntr[counter]; in pmevcntr_read()
1796 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_writefn()
1802 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_readfn()
1809 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawwrite()
1811 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_rawwrite()
1817 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawread()
1819 return env->cp15.c14_pmevcntr[counter]; in pmevcntr_rawread()
1825 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevcntr_write()
1830 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevcntr_read()
1837 env->cp15.c9_pmuserenr = value & 0xf; in pmuserenr_write()
1839 env->cp15.c9_pmuserenr = value & 1; in pmuserenr_write()
1848 env->cp15.c9_pminten |= value; in pmintenset_write()
1856 env->cp15.c9_pminten &= ~value; in pmintenclr_write()
1955 /* Clear all-context RES0 bits. */ in scr_write()
1957 changed = env->cp15.scr_el3 ^ value; in scr_write()
1958 env->cp15.scr_el3 = value; in scr_write()
1978 * scr_write will set the RES1 bits on an AArch64-only CPU. in scr_reset()
1979 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. in scr_reset()
2005 ri->secure & ARM_CP_SECSTATE_S); in ccsidr_read()
2007 return cpu->ccsidr[index]; in ccsidr_read()
2024 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { in isr_read()
2027 if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { in isr_read()
2032 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { in isr_read()
2036 if (cs->interrupt_request & CPU_INTERRUPT_NMI) { in isr_read()
2043 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { in isr_read()
2046 if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { in isr_read()
2051 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { in isr_read()
2057 if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { in isr_read()
2295 * MAIR can just read-as-written because we don't implement caches
2310 * For non-long-descriptor page tables these are PRRR and NMRR;
2311 * regardless they still act as reads-as-written for QEMU.
2314 * MAIR0/1 are defined separately from their 64-bit counterpart which
2408 env->teecr = value; in teecr_write()
2419 (env->cp15.hstr_el2 & HSTR_TTEE)) { in teecr_access()
2428 if (arm_current_el(env) == 0 && (env->teecr & 1)) { in teehbr_access()
2484 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; in arm_gt_cntfrq_reset()
2504 cntkctl = env->cp15.cnthctl_el2; in gt_cntfrq_access()
2506 cntkctl = env->cp15.c14_cntkctl; in gt_cntfrq_access()
2513 if (!isread && ri->state == ARM_CP_STATE_AA32 && in gt_cntfrq_access()
2515 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ in gt_cntfrq_access()
2542 return (extract32(env->cp15.cnthctl_el2, timeridx, 1) in gt_counter_access()
2547 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { in gt_counter_access()
2555 ? !extract32(env->cp15.cnthctl_el2, 10, 1) in gt_counter_access()
2556 : !extract32(env->cp15.cnthctl_el2, 0, 1))) { in gt_counter_access()
2560 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) { in gt_counter_access()
2580 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) in gt_timer_access()
2588 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { in gt_timer_access()
2597 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { in gt_timer_access()
2602 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { in gt_timer_access()
2608 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) { in gt_timer_access()
2657 if (!(env->cp15.scr_el3 & SCR_ST)) { in gt_stimer_access()
2680 CPUARMState *env = &cpu->env; in gt_update_irq()
2681 uint64_t cnthctl = env->cp15.cnthctl_el2; in gt_update_irq()
2684 int irqstate = (env->cp15.c14_timer[timeridx].ctl & 6) == 4; in gt_update_irq()
2696 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); in gt_update_irq()
2713 if ((env->cp15.scr_el3 & SCR_ECVEN) && in gt_phys_raw_cnt_offset()
2714 FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) && in gt_phys_raw_cnt_offset()
2717 return env->cp15.cntpoff_el2; in gt_phys_raw_cnt_offset()
2732 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; in gt_recalc_timer()
2734 if (gt->ctl & 1) { in gt_recalc_timer()
2736 * Timer enabled: calculate and set current ISTATUS, irq, and in gt_recalc_timer()
2740 cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); in gt_recalc_timer()
2741 uint64_t count = gt_get_countervalue(&cpu->env); in gt_recalc_timer()
2743 int istatus = count - offset >= gt->cval; in gt_recalc_timer()
2746 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); in gt_recalc_timer()
2750 * Next transition is when (count - offset) rolls back over to 0. in gt_recalc_timer()
2763 * Next transition is when (count - offset) == cval, i.e. in gt_recalc_timer()
2768 if (uadd64_overflow(gt->cval, offset, &nexttick)) { in gt_recalc_timer()
2774 * signed-64-bit range of a QEMUTimer -- in this case we just in gt_recalc_timer()
2779 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); in gt_recalc_timer()
2781 timer_mod(cpu->gt_timer[timeridx], nexttick); in gt_recalc_timer()
2786 gt->ctl &= ~4; in gt_recalc_timer()
2787 timer_del(cpu->gt_timer[timeridx]); in gt_recalc_timer()
2798 timer_del(cpu->gt_timer[timeridx]); in gt_timer_reset()
2803 return gt_get_countervalue(env) - gt_phys_cnt_offset(env); in gt_cnt_read()
2825 return env->cp15.cntvoff_el2; in gt_virt_cnt_offset()
2830 return gt_get_countervalue(env) - gt_virt_cnt_offset(env); in gt_virt_cnt_read()
2838 env->cp15.c14_timer[timeridx].cval = value; in gt_cval_write()
2857 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - in gt_tval_read()
2858 (gt_get_countervalue(env) - offset)); in gt_tval_read()
2878 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + in gt_tval_write()
2888 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; in gt_ctl_write()
2891 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); in gt_ctl_write()
2961 return env->cp15.c14_timer[timeridx].cval; in gt_phys_redir_cval_read()
2989 return env->cp15.c14_timer[timeridx].ctl; in gt_phys_redir_ctl_read()
3031 uint32_t oldval = env->cp15.cnthctl_el2; in gt_cnthctl_write()
3084 return env->cp15.c14_timer[timeridx].cval; in gt_virt_redir_cval_read()
3112 return env->cp15.c14_timer[timeridx].ctl; in gt_virt_redir_ctl_read()
3243 * Note that CNTFRQ is purely reads-as-written for the benefit
3265 /* per-timer control */
3411 * Secure timer -- this is actually restricted to only EL3
3412 * and configurably Secure-EL1 via the accessfn.
3441 * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
3472 !(env->cp15.scr_el3 & SCR_ECVEN)) { in gt_cntpoff_access()
3499 * In user-mode most of the generic timer registers are inaccessible
3508 * Currently we have no support for QEMUTimer in linux-user so we in gt_virt_cnt_read()
3518 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
3555 /* get_phys_addr() isn't present for user-mode-only targets */
3560 if (ri->opc2 & 4) { in ats_access()
3569 if (env->cp15.scr_el3 & SCR_EEL2) { in ats_access()
3584 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC in par_el1_shareability()
3585 * memory -- see pseudocode PAREncodeShareability(). in par_el1_shareability()
3587 if (((res->cacheattrs.attrs & 0xf0) == 0) || in par_el1_shareability()
3588 res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { in par_el1_shareability()
3591 return res->cacheattrs.shareability; in par_el1_shareability()
3636 * and HPFAR_EL2 holds the faulting IPA. in do_ats_write()
3639 (env->cp15.scr_el3 & SCR_EA)) { in do_ats_write()
3642 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; in do_ats_write()
3644 env->cp15.hpfar_el2 |= HPFAR_NS; in do_ats_write()
3682 env->exception.vaddress = value; in do_ats_write()
3683 env->exception.fsr = fsr; in do_ats_write()
3694 * 32-bit or the 64-bit PAR format in do_ats_write()
3698 * * The Non-secure TTBCR.EAE bit is set to 1 in do_ats_write()
3711 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); in do_ats_write()
3719 /* Create a 64-bit PAR */ in do_ats_write()
3744 * Convert it to a 32-bit PAR. in do_ats_write()
3771 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write()
3777 switch (ri->opc2 & 6) { in ats_write()
3782 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
3789 g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ in ats_write()
3792 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
3809 g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ in ats_write()
3846 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats1h_write()
3870 if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { in at_e012_access()
3880 !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { in at_s1e2_access()
3899 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write64()
3906 switch (ri->opc2 & 6) { in ats_write64()
3908 switch (ri->opc1) { in ats_write64()
3910 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write64()
3942 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss); in ats_write64()
3983 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); in pmsav5_data_ap_write()
3988 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); in pmsav5_data_ap_read()
3994 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); in pmsav5_insn_ap_write()
3999 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); in pmsav5_insn_ap_read()
4010 u32p += env->pmsav7.rnr[M_REG_NS]; in pmsav7_read()
4024 u32p += env->pmsav7.rnr[M_REG_NS]; in pmsav7_write()
4025 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in pmsav7_write()
4033 uint32_t nrgs = cpu->pmsav7_dregion; in pmsav7_rgnr_write()
4050 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in prbar_write()
4051 env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prbar_write()
4056 return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in prbar_read()
4064 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in prlar_write()
4065 env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prlar_write()
4070 return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in prlar_read()
4082 if (value >= cpu->pmsav7_dregion) { in prselr_write()
4086 env->pmsav7.rnr[M_REG_NS] = value; in prselr_write()
4094 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in hprbar_write()
4095 env->pmsav8.hprbar[env->pmsav8.hprselr] = value; in hprbar_write()
4100 return env->pmsav8.hprbar[env->pmsav8.hprselr]; in hprbar_read()
4108 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in hprlar_write()
4109 env->pmsav8.hprlar[env->pmsav8.hprselr] = value; in hprlar_write()
4114 return env->pmsav8.hprlar[env->pmsav8.hprselr]; in hprlar_read()
4125 int rmax = MIN(cpu->pmsav8r_hdregion, 32); in hprenr_write()
4128 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in hprenr_write()
4130 /* Register alias is only valid for first 32 indexes */ in hprenr_write()
4133 env->pmsav8.hprlar[n] = deposit32( in hprenr_write()
4134 env->pmsav8.hprlar[n], 0, 1, bit); in hprenr_write()
4144 /* Register alias is only valid for first 32 indexes */ in hprenr_read()
4145 for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { in hprenr_read()
4146 if (env->pmsav8.hprlar[n] & 0x1) { in hprenr_read()
4162 if (value >= cpu->pmsav8r_hdregion) { in hprselr_write()
4166 env->pmsav8.hprselr = value; in hprselr_write()
4173 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | in pmsav8r_regn_write()
4174 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_write()
4176 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in pmsav8r_regn_write()
4178 if (ri->opc1 & 4) { in pmsav8r_regn_write()
4179 if (index >= cpu->pmsav8r_hdregion) { in pmsav8r_regn_write()
4182 if (ri->opc2 & 0x1) { in pmsav8r_regn_write()
4183 env->pmsav8.hprlar[index] = value; in pmsav8r_regn_write()
4185 env->pmsav8.hprbar[index] = value; in pmsav8r_regn_write()
4188 if (index >= cpu->pmsav7_dregion) { in pmsav8r_regn_write()
4191 if (ri->opc2 & 0x1) { in pmsav8r_regn_write()
4192 env->pmsav8.rlar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4194 env->pmsav8.rbar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4202 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | in pmsav8r_regn_read()
4203 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_read()
4205 if (ri->opc1 & 4) { in pmsav8r_regn_read()
4206 if (index >= cpu->pmsav8r_hdregion) { in pmsav8r_regn_read()
4209 if (ri->opc2 & 0x1) { in pmsav8r_regn_read()
4210 return env->pmsav8.hprlar[index]; in pmsav8r_regn_read()
4212 return env->pmsav8.hprbar[index]; in pmsav8r_regn_read()
4215 if (index >= cpu->pmsav7_dregion) { in pmsav8r_regn_read()
4218 if (ri->opc2 & 0x1) { in pmsav8r_regn_read()
4219 return env->pmsav8.rlar[M_REG_NS][index]; in pmsav8r_regn_read()
4221 return env->pmsav8.rbar[M_REG_NS][index]; in pmsav8r_regn_read()
4264 * because the PMSAv7 is also used by M-profile CPUs, which do
4348 * using Long-descriptor translation table format in vmsa_ttbcr_write()
4355 * Short-descriptor translation table format. in vmsa_ttbcr_write()
4386 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ in vmsa_ttbr_write()
4509 env->cp15.c15_ticonfig = value & 0xe7; in omap_ticonfig_write()
4511 env->cp15.c0_cpuid = (value & (1 << 5)) ? in omap_ticonfig_write()
4518 env->cp15.c15_threadid = value & 0xffff; in omap_threadid_write()
4524 /* Wait-for-interrupt (deprecated) */ in omap_wfi_write()
4535 env->cp15.c15_i_max = 0x000; in omap_cachemaint_write()
4536 env->cp15.c15_i_min = 0xff0; in omap_cachemaint_write()
4582 env->cp15.c15_cpar = value & 0x3fff; in xscale_cpar_write()
4595 * XScale specific cache-lockdown: since we have no cache we NOP these
4615 * implementation of this implementation-defined space.
4655 * The cache test-and-clean instructions always return (1 << 30)
4679 return env->cp15.vpidr_el2; in midr_read()
4687 uint64_t mpidr = cpu->mp_affinity; in mpidr_read_val()
4692 * Cores which are uniprocessor (non-coherent) in mpidr_read_val()
4694 * bit 30. (For instance, Cortex-R5). in mpidr_read_val()
4696 if (cpu->mp_is_up) { in mpidr_read_val()
4708 return env->cp15.vmpidr_el2; in mpidr_read()
4777 env->daif = value & PSTATE_DAIF; in aa64_daif_write()
4782 return env->pstate & PSTATE_PAN; in aa64_pan_read()
4788 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); in aa64_pan_write()
4800 return env->pstate & PSTATE_UAO; in aa64_uao_read()
4806 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); in aa64_uao_write()
4818 return env->pstate & PSTATE_DIT; in aa64_dit_read()
4824 env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); in aa64_dit_write()
4836 return env->pstate & PSTATE_SSBS; in aa64_ssbs_read()
4842 env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); in aa64_ssbs_write()
4908 * Page D4-1736 (DDI0487A.b)
4946 /* Return 56 if TBI is enabled, 64 otherwise. */
5082 * flush-last-level-only. in tlbi_aa64_vae2_write()
5098 * flush-last-level-only. in tlbi_aa64_vae3_write()
5124 * since we don't support flush-for-specific-ASID-only or in tlbi_aa64_vae1_write()
5125 * flush-last-level-only. in tlbi_aa64_vae1_write()
5296 * since we don't support flush-for-specific-ASID-only or in tlbi_aa64_rvae1_write()
5297 * flush-last-level-only. in tlbi_aa64_rvae1_write()
5312 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer in tlbi_aa64_rvae1is_write()
5326 * since we don't support flush-for-specific-ASID-only or in tlbi_aa64_rvae2_write()
5327 * flush-last-level-only. in tlbi_aa64_rvae2_write()
5343 * since we don't support flush-for-specific-ASID-only, in tlbi_aa64_rvae2is_write()
5344 * flush-last-level-only or inner/outer shareable specific flushes. in tlbi_aa64_rvae2is_write()
5358 * since we don't support flush-for-specific-ASID-only or in tlbi_aa64_rvae3_write()
5359 * flush-last-level-only. in tlbi_aa64_rvae3_write()
5372 * since we don't support flush-for-specific-ASID-only, in tlbi_aa64_rvae3is_write()
5373 * flush-last-level-only or inner/outer specific flushes. in tlbi_aa64_rvae3is_write()
5404 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { in aa64_zva_access()
5408 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { in aa64_zva_access()
5431 return cpu->dcz_blocksize | dzp_bit; in aa64_dczid_read()
5437 if (!(env->pstate & PSTATE_SP)) { in sp_el0_access()
5449 return env->pstate & PSTATE_SP; in spsel_read()
5462 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { in sctlr_write()
5469 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { in sctlr_write()
5470 if (ri->opc1 == 6) { /* SCTLR_EL3 */ in sctlr_write()
5491 if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { in sctlr_write()
5510 bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; in mdcr_el3_write()
5515 env->cp15.mdcr_el3 = value; in mdcr_el3_write()
5536 bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; in mdcr_el2_write()
5541 env->cp15.mdcr_el2 = value; in mdcr_el2_write()
5562 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5578 icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; in ic_ivau_write()
5592 * Minimal set of EL0-visible registers. This will need to be expanded
5621 /* Avoid overhead of an access check that always passes in user-mode */
6000 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { in do_hcr_write()
6057 * HCR_PTW forbids certain page-table setups in do_hcr_write()
6063 if ((env->cp15.hcr_el2 ^ value) & in do_hcr_write()
6067 env->cp15.hcr_el2 = value; in do_hcr_write()
6099 value = deposit64(env->cp15.hcr_el2, 32, 32, value); in hcr_writehigh()
6107 value = deposit64(env->cp15.hcr_el2, 0, 32, value); in hcr_writelow()
6118 uint64_t ret = env->cp15.hcr_el2; in arm_hcr_el2_eff_secstate()
6124 * "This register has no effect if EL2 is not enabled in the in arm_hcr_el2_eff_secstate()
6125 * current Security state". This is ARMv8.4-SecEL2 speak for in arm_hcr_el2_eff_secstate()
6132 * on a per-field basis. In current QEMU, this is condition in arm_hcr_el2_eff_secstate()
6144 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. in arm_hcr_el2_eff_secstate()
6150 * These bits are up-to-date as of ARMv8.6. in arm_hcr_el2_eff_secstate()
6152 * For HCR2, list those that are valid. in arm_hcr_el2_eff_secstate()
6161 /* These bits are up-to-date as of ARMv8.6. */ in arm_hcr_el2_eff_secstate()
6209 if ((env->cp15.hcr_el2 & mask) != mask) { in el_is_in_host()
6239 env->cp15.hcrx_el2 = value & valid_mask; in hcrx_write()
6264 && !(env->cp15.scr_el3 & SCR_HXEN)) { in access_hxen()
6285 * If EL2 is not enabled in the current security state, then the in arm_hcrx_el2_eff()
6287 * For the moment, we treat the EL2-disabled case as taking in arm_hcrx_el2_eff()
6288 * priority over the HXEn-disabled case. This is true for the only in arm_hcrx_el2_eff()
6296 /* MSCEn behaves as 1 if EL2 is not enabled */ in arm_hcrx_el2_eff()
6301 if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { in arm_hcrx_el2_eff()
6304 return env->cp15.hcrx_el2; in arm_hcrx_el2_eff()
6311 * For A-profile AArch32 EL3, if NSACR.CP10 in cptr_el2_write()
6315 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cptr_el2_write()
6317 value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); in cptr_el2_write()
6319 env->cp15.cptr_el[2] = value; in cptr_el2_write()
6325 * For A-profile AArch32 EL3, if NSACR.CP10 in cptr_el2_read()
6328 uint64_t value = env->cp15.cptr_el[2]; in cptr_el2_read()
6331 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cptr_el2_read()
6504 * Unlike the other EL2-related AT operations, these must
6629 if (env->cp15.scr_el3 & SCR_EEL2) { in nsacr_access()
6760 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) { in access_el1nvpct()
6772 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) { in access_el1nvvct()
6791 ri = ri->opaque; in el2_e2h_read()
6792 readfn = ri->readfn; in el2_e2h_read()
6794 readfn = ri->orig_readfn; in el2_e2h_read()
6809 ri = ri->opaque; in el2_e2h_write()
6810 writefn = ri->writefn; in el2_e2h_write()
6812 writefn = ri->orig_writefn; in el2_e2h_write()
6823 return ri->orig_readfn(env, ri->opaque); in el2_e2h_e12_read()
6830 return ri->orig_writefn(env, ri->opaque, value); in el2_e2h_e12_write()
6850 if (ri->orig_accessfn) { in el2_e2h_e12_access()
6851 return ri->orig_accessfn(env, ri->opaque, isread); in el2_e2h_e12_access()
6918 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ in define_arm_vh_e2h_redirects_aliases()
6919 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ in define_arm_vh_e2h_redirects_aliases()
6930 if (a->feature && !a->feature(&cpu->isar)) { in define_arm_vh_e2h_redirects_aliases()
6934 src_reg = g_hash_table_lookup(cpu->cp_regs, in define_arm_vh_e2h_redirects_aliases()
6935 (gpointer)(uintptr_t)a->src_key); in define_arm_vh_e2h_redirects_aliases()
6936 dst_reg = g_hash_table_lookup(cpu->cp_regs, in define_arm_vh_e2h_redirects_aliases()
6937 (gpointer)(uintptr_t)a->dst_key); in define_arm_vh_e2h_redirects_aliases()
6941 /* Cross-compare names to detect typos in the keys. */ in define_arm_vh_e2h_redirects_aliases()
6942 g_assert(strcmp(src_reg->name, a->src_name) == 0); in define_arm_vh_e2h_redirects_aliases()
6943 g_assert(strcmp(dst_reg->name, a->dst_name) == 0); in define_arm_vh_e2h_redirects_aliases()
6946 g_assert(src_reg->opaque == NULL); in define_arm_vh_e2h_redirects_aliases()
6951 new_reg->name = a->new_name; in define_arm_vh_e2h_redirects_aliases()
6952 new_reg->type |= ARM_CP_ALIAS; in define_arm_vh_e2h_redirects_aliases()
6954 new_reg->access &= PL2_RW | PL3_RW; in define_arm_vh_e2h_redirects_aliases()
6956 new_reg->crn = (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) in define_arm_vh_e2h_redirects_aliases()
6958 new_reg->crm = (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) in define_arm_vh_e2h_redirects_aliases()
6960 new_reg->opc0 = (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) in define_arm_vh_e2h_redirects_aliases()
6962 new_reg->opc1 = (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) in define_arm_vh_e2h_redirects_aliases()
6964 new_reg->opc2 = (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) in define_arm_vh_e2h_redirects_aliases()
6966 new_reg->opaque = src_reg; in define_arm_vh_e2h_redirects_aliases()
6967 new_reg->orig_readfn = src_reg->readfn ?: raw_read; in define_arm_vh_e2h_redirects_aliases()
6968 new_reg->orig_writefn = src_reg->writefn ?: raw_write; in define_arm_vh_e2h_redirects_aliases()
6969 new_reg->orig_accessfn = src_reg->accessfn; in define_arm_vh_e2h_redirects_aliases()
6970 if (!new_reg->raw_readfn) { in define_arm_vh_e2h_redirects_aliases()
6971 new_reg->raw_readfn = raw_read; in define_arm_vh_e2h_redirects_aliases()
6973 if (!new_reg->raw_writefn) { in define_arm_vh_e2h_redirects_aliases()
6974 new_reg->raw_writefn = raw_write; in define_arm_vh_e2h_redirects_aliases()
6976 new_reg->readfn = el2_e2h_e12_read; in define_arm_vh_e2h_redirects_aliases()
6977 new_reg->writefn = el2_e2h_e12_write; in define_arm_vh_e2h_redirects_aliases()
6978 new_reg->accessfn = el2_e2h_e12_access; in define_arm_vh_e2h_redirects_aliases()
6985 if (new_reg->nv2_redirect_offset) { in define_arm_vh_e2h_redirects_aliases()
6986 assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1); in define_arm_vh_e2h_redirects_aliases()
6987 new_reg->nv2_redirect_offset &= ~NV2_REDIR_NV1; in define_arm_vh_e2h_redirects_aliases()
6988 new_reg->nv2_redirect_offset |= NV2_REDIR_NO_NV1; in define_arm_vh_e2h_redirects_aliases()
6991 ok = g_hash_table_insert(cpu->cp_regs, in define_arm_vh_e2h_redirects_aliases()
6992 (gpointer)(uintptr_t)a->new_key, new_reg); in define_arm_vh_e2h_redirects_aliases()
6995 src_reg->opaque = dst_reg; in define_arm_vh_e2h_redirects_aliases()
6996 src_reg->orig_readfn = src_reg->readfn ?: raw_read; in define_arm_vh_e2h_redirects_aliases()
6997 src_reg->orig_writefn = src_reg->writefn ?: raw_write; in define_arm_vh_e2h_redirects_aliases()
6998 if (!src_reg->raw_readfn) { in define_arm_vh_e2h_redirects_aliases()
6999 src_reg->raw_readfn = raw_read; in define_arm_vh_e2h_redirects_aliases()
7001 if (!src_reg->raw_writefn) { in define_arm_vh_e2h_redirects_aliases()
7002 src_reg->raw_writefn = raw_write; in define_arm_vh_e2h_redirects_aliases()
7004 src_reg->readfn = el2_e2h_read; in define_arm_vh_e2h_redirects_aliases()
7005 src_reg->writefn = el2_e2h_write; in define_arm_vh_e2h_redirects_aliases()
7020 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { in ctr_el0_access()
7024 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { in ctr_el0_access()
7055 if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { in access_terr()
7066 return env->cp15.vdisr_el2; in disr_read()
7068 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { in disr_read()
7071 return env->cp15.disr_el1; in disr_read()
7079 env->cp15.vdisr_el2 = val; in disr_write()
7082 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { in disr_write()
7085 env->cp15.disr_el1 = val; in disr_write()
7107 * These registers have fine-grained trap bits, but UNDEF-to-EL1
7108 * is higher priority than FGT-to-EL2 so we do not need to list them
7145 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { in sve_exception_el()
7159 if (env->cp15.hcr_el2 & HCR_E2H) { in sve_exception_el()
7160 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { in sve_exception_el()
7162 if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { in sve_exception_el()
7171 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { in sve_exception_el()
7179 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { in sve_exception_el()
7194 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { in sme_exception_el()
7208 if (env->cp15.hcr_el2 & HCR_E2H) { in sme_exception_el()
7209 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { in sme_exception_el()
7211 if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { in sme_exception_el()
7220 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { in sme_exception_el()
7228 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in sme_exception_el()
7236 * Given that SVE is enabled, return the vector length for EL.
7241 uint64_t *cr = env->vfp.zcr_el; in sve_vqm1_for_el_sm()
7242 uint32_t map = cpu->sve_vq.map; in sve_vqm1_for_el_sm()
7243 uint32_t len = ARM_MAX_VQ - 1; in sve_vqm1_for_el_sm()
7246 cr = env->vfp.smcr_el; in sve_vqm1_for_el_sm()
7247 map = cpu->sme_vq.map; in sve_vqm1_for_el_sm()
7262 return 31 - clz32(map); in sve_vqm1_for_el_sm()
7265 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ in sve_vqm1_for_el_sm()
7267 return ctz32(cpu->sme_vq.map); in sve_vqm1_for_el_sm()
7272 return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); in sve_vqm1_for_el()
7287 * Because we arrived here, we know both FP and SVE are enabled; in zcr_write()
7330 && !(env->cp15.scr_el3 & SCR_ENTP2)) { in access_tpidr2()
7342 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in access_smprimap()
7353 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in access_smpri()
7362 memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); in arm_reset_sve_state()
7364 memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); in arm_reset_sve_state()
7370 uint64_t change = (env->svcr ^ new) & mask; in aarch64_set_svcr()
7375 env->svcr ^= change; in aarch64_set_svcr()
7390 memset(env->zarray, 0, sizeof(env->zarray)); in aarch64_set_svcr()
7401 aarch64_set_svcr(env, value, -1); in svcr_write()
7419 * apply the narrower SVL to the Zregs and Pregs -- see the comment in smcr_write()
7496 env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); in gpccr_write()
7501 env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, in gpccr_reset()
7502 env_archcpu(env)->reset_l0gptsz); in gpccr_reset()
7560 env->pstate = (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLINT); in aa64_allint_write()
7565 return env->pstate & PSTATE_ALLINT; in aa64_allint_read()
7596 unsigned int i, pmcrn = pmu_num_counters(&cpu->env); in define_pmu_regs()
7614 .resetvalue = cpu->isar.reset_pmcr_el0, in define_pmu_regs()
7667 .resetvalue = extract64(cpu->pmceid0, 32, 32) }, in define_pmu_regs()
7672 .resetvalue = extract64(cpu->pmceid1, 32, 32) }, in define_pmu_regs()
7698 uint64_t pfr1 = cpu->isar.id_pfr1; in id_pfr1_read()
7700 if (env->gicv3state) { in id_pfr1_read()
7709 uint64_t pfr0 = cpu->isar.id_aa64pfr0; in id_aa64pfr0_read()
7711 if (env->gicv3state) { in id_aa64pfr0_read()
7730 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { in access_lor_ns()
7747 * A trivial implementation of ARMv8.1-LOR leaves all of these
7792 !(env->cp15.scr_el3 & SCR_APK)) { in access_pauth()
8061 env->NF = env->CF = env->VF = 0, env->ZF = 1; in rndr_readfn()
8067 * timed-out indication to the guest. There is no reason in rndr_readfn()
8072 ri->name, error_get_pretty(err)); in rndr_readfn()
8075 env->ZF = 0; /* NZCF = 0100 */ in rndr_readfn()
8081 /* We do not support re-seeding, so the two registers operate the same. */
8098 /* CTR_EL0 System register -> DminLine, bits [19:16] */ in dccvap_writefn()
8099 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); in dccvap_writefn()
8101 uint64_t vaddr = vaddr_in & ~(dline_size - 1); in dccvap_writefn()
8165 !(env->cp15.scr_el3 & SCR_ATA)) { in access_mte()
8188 * if NV2 is enabled then we will redirect this to TFSR_EL1 in access_tfsr_el2()
8205 !(env->cp15.scr_el3 & SCR_ATA)) { in access_tfsr_el2()
8213 return env->pstate & PSTATE_TCO; in tco_read()
8218 env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); in tco_write()
8339 /* Avoid overhead of an access check that always passes in user-mode */
8348 /* Avoid overhead of an access check that always passes in user-mode */
8362 if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { in access_scxtnum()
8368 } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { in access_scxtnum()
8376 && !(env->cp15.scr_el3 & SCR_ENSCXT)) { in access_scxtnum()
8420 arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) { in access_fgt()
8459 * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything in vncr_write()
8460 * about the RESS bits at the top -- we choose the "generate an EL2 in vncr_write()
8464 env->cp15.vncr_el2 = value & ~0xfffULL; in vncr_write()
8580 (env->cp15.hstr_el2 & HSTR_TJDBX)) { in access_joscr_jmcr()
8702 * is non-zero, which is never for ARMv7, optionally in ARMv8
8722 CPUARMState *env = &cpu->env; in register_cp_regs_for_features()
8744 .resetvalue = cpu->isar.id_pfr0 }, in register_cp_regs_for_features()
8755 .resetvalue = cpu->isar.id_pfr1, in register_cp_regs_for_features()
8767 .resetvalue = cpu->isar.id_dfr0 }, in register_cp_regs_for_features()
8772 .resetvalue = cpu->id_afr0 }, in register_cp_regs_for_features()
8777 .resetvalue = cpu->isar.id_mmfr0 }, in register_cp_regs_for_features()
8782 .resetvalue = cpu->isar.id_mmfr1 }, in register_cp_regs_for_features()
8787 .resetvalue = cpu->isar.id_mmfr2 }, in register_cp_regs_for_features()
8792 .resetvalue = cpu->isar.id_mmfr3 }, in register_cp_regs_for_features()
8797 .resetvalue = cpu->isar.id_isar0 }, in register_cp_regs_for_features()
8802 .resetvalue = cpu->isar.id_isar1 }, in register_cp_regs_for_features()
8807 .resetvalue = cpu->isar.id_isar2 }, in register_cp_regs_for_features()
8812 .resetvalue = cpu->isar.id_isar3 }, in register_cp_regs_for_features()
8817 .resetvalue = cpu->isar.id_isar4 }, in register_cp_regs_for_features()
8822 .resetvalue = cpu->isar.id_isar5 }, in register_cp_regs_for_features()
8827 .resetvalue = cpu->isar.id_mmfr4 }, in register_cp_regs_for_features()
8832 .resetvalue = cpu->isar.id_isar6 }, in register_cp_regs_for_features()
8856 .resetvalue = cpu->clidr in register_cp_regs_for_features()
8887 .resetvalue = cpu->isar.id_aa64pfr0 in register_cp_regs_for_features()
8899 .resetvalue = cpu->isar.id_aa64pfr1}, in register_cp_regs_for_features()
8914 .resetvalue = cpu->isar.id_aa64zfr0 }, in register_cp_regs_for_features()
8919 .resetvalue = cpu->isar.id_aa64smfr0 }, in register_cp_regs_for_features()
8934 .resetvalue = cpu->isar.id_aa64dfr0 }, in register_cp_regs_for_features()
8939 .resetvalue = cpu->isar.id_aa64dfr1 }, in register_cp_regs_for_features()
8954 .resetvalue = cpu->id_aa64afr0 }, in register_cp_regs_for_features()
8959 .resetvalue = cpu->id_aa64afr1 }, in register_cp_regs_for_features()
8974 .resetvalue = cpu->isar.id_aa64isar0 }, in register_cp_regs_for_features()
8979 .resetvalue = cpu->isar.id_aa64isar1 }, in register_cp_regs_for_features()
8984 .resetvalue = cpu->isar.id_aa64isar2 }, in register_cp_regs_for_features()
9014 .resetvalue = cpu->isar.id_aa64mmfr0 }, in register_cp_regs_for_features()
9019 .resetvalue = cpu->isar.id_aa64mmfr1 }, in register_cp_regs_for_features()
9024 .resetvalue = cpu->isar.id_aa64mmfr2 }, in register_cp_regs_for_features()
9029 .resetvalue = cpu->isar.id_aa64mmfr3 }, in register_cp_regs_for_features()
9054 .resetvalue = cpu->isar.mvfr0 }, in register_cp_regs_for_features()
9059 .resetvalue = cpu->isar.mvfr1 }, in register_cp_regs_for_features()
9064 .resetvalue = cpu->isar.mvfr2 }, in register_cp_regs_for_features()
9089 * being filled with AArch64-view-of-AArch32-ID-register in register_cp_regs_for_features()
9101 .resetvalue = cpu->isar.id_pfr2 }, in register_cp_regs_for_features()
9106 .resetvalue = cpu->isar.id_dfr1 }, in register_cp_regs_for_features()
9111 .resetvalue = cpu->isar.id_mmfr5 }, in register_cp_regs_for_features()
9121 .resetvalue = extract64(cpu->pmceid0, 0, 32) }, in register_cp_regs_for_features()
9126 .resetvalue = cpu->pmceid0 }, in register_cp_regs_for_features()
9131 .resetvalue = extract64(cpu->pmceid1, 0, 32) }, in register_cp_regs_for_features()
9136 .resetvalue = cpu->pmceid1 }, in register_cp_regs_for_features()
9267 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32. in register_cp_regs_for_features()
9268 * For pre-v8 cores there are RAZ patterns for these in in register_cp_regs_for_features()
9271 * to also cover c0, 0, c{8-15}, {0-7}. in register_cp_regs_for_features()
9273 * c4-c7 is where the AArch64 ID registers live (and we've in register_cp_regs_for_features()
9274 * already defined those in v8_idregs[]), and c8-c15 are not in register_cp_regs_for_features()
9293 * if EL2 is missing but EL3 is enabled, mostly these become in register_cp_regs_for_features()
9304 .resetvalue = cpu->midr, in register_cp_regs_for_features()
9309 .access = PL2_RW, .resetvalue = cpu->midr, in register_cp_regs_for_features()
9388 .resetvalue = cpu->reset_sctlr }, in register_cp_regs_for_features()
9445 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ in register_cp_regs_for_features()
9480 * When LPAE exists this 32-bit PAR register is an alias of the in register_cp_regs_for_features()
9481 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[] in register_cp_regs_for_features()
9517 * cp15 crn=0 to be writes-ignored, whereas for other cores they should in register_cp_regs_for_features()
9518 * be read-only (ie write causes UNDEF exception). in register_cp_regs_for_features()
9523 * Pre-v8 MIDR space. in register_cp_regs_for_features()
9534 .access = PL1_R, .resetvalue = cpu->midr, in register_cp_regs_for_features()
9559 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, in register_cp_regs_for_features()
9566 .access = PL1_R, .resetvalue = cpu->midr }, in register_cp_regs_for_features()
9572 .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, in register_cp_regs_for_features()
9577 .access = PL1_R, .resetvalue = cpu->midr in register_cp_regs_for_features()
9580 /* These are common to v8 and pre-v8 */ in register_cp_regs_for_features()
9584 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, in register_cp_regs_for_features()
9589 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, in register_cp_regs_for_features()
9590 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ in register_cp_regs_for_features()
9610 .resetvalue = cpu->pmsav7_dregion << 8 in register_cp_regs_for_features()
9617 .resetvalue = cpu->pmsav8r_hdregion in register_cp_regs_for_features()
9675 /* Register alias is only valid for first 32 indexes */ in register_cp_regs_for_features()
9676 for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { in register_cp_regs_for_features()
9705 /* Register alias is only valid for first 32 indexes */ in register_cp_regs_for_features()
9706 for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { in register_cp_regs_for_features()
9762 .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, in register_cp_regs_for_features()
9780 * CBAR is IMPDEF, but common on Arm Cortex-A implementations. in register_cp_regs_for_features()
9782 * (1) older 32-bit only cores have a simple 32-bit CBAR in register_cp_regs_for_features()
9783 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a in register_cp_regs_for_features()
9784 * 32-bit register visible to AArch32 at a different encoding in register_cp_regs_for_features()
9786 * be able to squash a 64-bit address into the 32-bit view. in register_cp_regs_for_features()
9788 * in future if we support AArch32-only configs of some of the in register_cp_regs_for_features()
9794 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) in register_cp_regs_for_features()
9795 | extract64(cpu->reset_cbar, 32, 12); in register_cp_regs_for_features()
9804 .access = PL1_R, .resetvalue = cpu->reset_cbar }, in register_cp_regs_for_features()
9813 .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar, in register_cp_regs_for_features()
9851 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, in register_cp_regs_for_features()
9857 * arch/arm/mach-pxa/sleep.S expects two instructions following in register_cp_regs_for_features()
9946 * If full MTE is enabled, add all of the system registers. in register_cp_regs_for_features()
9947 * If only "instructions available at EL0" are enabled, in register_cp_regs_for_features()
9955 .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, in register_cp_regs_for_features()
10018 CPUARMState *env = &cpu->env; in add_cpreg_to_hashtable()
10021 bool is64 = r->type & ARM_CP_64BIT; in add_cpreg_to_hashtable()
10023 int cp = r->cp; in add_cpreg_to_hashtable()
10030 if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
10033 key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); in add_cpreg_to_hashtable()
10038 * cp == 0 as equivalent to the value for "standard guest-visible in add_cpreg_to_hashtable()
10040 * in their AArch64 view (the .cp value may be non-zero for the in add_cpreg_to_hashtable()
10043 if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
10046 key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); in add_cpreg_to_hashtable()
10053 if (!(r->type & ARM_CP_OVERRIDE)) { in add_cpreg_to_hashtable()
10054 const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); in add_cpreg_to_hashtable()
10056 assert(oldreg->type & ARM_CP_OVERRIDE); in add_cpreg_to_hashtable()
10071 int min_el = ctz32(r->access) / 2; in add_cpreg_to_hashtable()
10073 if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { in add_cpreg_to_hashtable()
10076 make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); in add_cpreg_to_hashtable()
10081 if ((r->access & max_el) == 0) { in add_cpreg_to_hashtable()
10090 r2->name = memcpy(r2 + 1, name, name_len); in add_cpreg_to_hashtable()
10096 r2->cp = cp; in add_cpreg_to_hashtable()
10097 r2->crm = crm; in add_cpreg_to_hashtable()
10098 r2->opc1 = opc1; in add_cpreg_to_hashtable()
10099 r2->opc2 = opc2; in add_cpreg_to_hashtable()
10100 r2->state = state; in add_cpreg_to_hashtable()
10101 r2->secure = secstate; in add_cpreg_to_hashtable()
10103 r2->opaque = opaque; in add_cpreg_to_hashtable()
10108 int old_special = r2->type & ARM_CP_SPECIAL_MASK; in add_cpreg_to_hashtable()
10115 r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; in add_cpreg_to_hashtable()
10118 * special cases like VPIDR_EL2 which have a constant non-zero in add_cpreg_to_hashtable()
10121 if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { in add_cpreg_to_hashtable()
10122 r2->resetvalue = 0; in add_cpreg_to_hashtable()
10129 r2->readfn = NULL; in add_cpreg_to_hashtable()
10130 r2->writefn = NULL; in add_cpreg_to_hashtable()
10131 r2->raw_readfn = NULL; in add_cpreg_to_hashtable()
10132 r2->raw_writefn = NULL; in add_cpreg_to_hashtable()
10133 r2->resetfn = NULL; in add_cpreg_to_hashtable()
10134 r2->fieldoffset = 0; in add_cpreg_to_hashtable()
10135 r2->bank_fieldoffsets[0] = 0; in add_cpreg_to_hashtable()
10136 r2->bank_fieldoffsets[1] = 0; in add_cpreg_to_hashtable()
10138 bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; in add_cpreg_to_hashtable()
10146 r2->fieldoffset = r->bank_fieldoffsets[ns]; in add_cpreg_to_hashtable()
10152 * reset the 32-bit instance in certain cases: in add_cpreg_to_hashtable()
10154 * 1) If the register has both 32-bit and 64-bit instances in add_cpreg_to_hashtable()
10155 * then we can count on the 64-bit instance taking care in add_cpreg_to_hashtable()
10156 * of the non-secure bank. in add_cpreg_to_hashtable()
10157 * 2) If ARMv8 is enabled then we can count on a 64-bit in add_cpreg_to_hashtable()
10159 * that separate 32 and 64-bit definitions are provided. in add_cpreg_to_hashtable()
10161 if ((r->state == ARM_CP_STATE_BOTH && ns) || in add_cpreg_to_hashtable()
10163 r2->type |= ARM_CP_ALIAS; in add_cpreg_to_hashtable()
10165 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
10168 * migration of the non-secure instance. in add_cpreg_to_hashtable()
10170 r2->type |= ARM_CP_ALIAS; in add_cpreg_to_hashtable()
10174 r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { in add_cpreg_to_hashtable()
10175 r2->fieldoffset += sizeof(uint32_t); in add_cpreg_to_hashtable()
10185 * never migratable and not even raw-accessible. in add_cpreg_to_hashtable()
10187 if (r2->type & ARM_CP_SPECIAL_MASK) { in add_cpreg_to_hashtable()
10188 r2->type |= ARM_CP_NO_RAW; in add_cpreg_to_hashtable()
10190 if (((r->crm == CP_ANY) && crm != 0) || in add_cpreg_to_hashtable()
10191 ((r->opc1 == CP_ANY) && opc1 != 0) || in add_cpreg_to_hashtable()
10192 ((r->opc2 == CP_ANY) && opc2 != 0)) { in add_cpreg_to_hashtable()
10193 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; in add_cpreg_to_hashtable()
10201 if (!(r2->type & ARM_CP_NO_RAW)) { in add_cpreg_to_hashtable()
10205 g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); in add_cpreg_to_hashtable()
10222 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard in define_one_arm_cp_reg_with_opaque()
10231 * Only registers visible in AArch64 may set r->opc0; opc0 cannot in define_one_arm_cp_reg_with_opaque()
10237 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; in define_one_arm_cp_reg_with_opaque()
10238 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; in define_one_arm_cp_reg_with_opaque()
10239 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; in define_one_arm_cp_reg_with_opaque()
10240 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; in define_one_arm_cp_reg_with_opaque()
10241 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; in define_one_arm_cp_reg_with_opaque()
10242 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; in define_one_arm_cp_reg_with_opaque()
10246 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); in define_one_arm_cp_reg_with_opaque()
10248 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); in define_one_arm_cp_reg_with_opaque()
10250 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); in define_one_arm_cp_reg_with_opaque()
10253 * (M-profile or v7A-and-earlier only) for implementation defined in define_one_arm_cp_reg_with_opaque()
10259 switch (r->state) { in define_one_arm_cp_reg_with_opaque()
10262 if (r->cp == 0) { in define_one_arm_cp_reg_with_opaque()
10267 if (arm_feature(&cpu->env, ARM_FEATURE_V8) && in define_one_arm_cp_reg_with_opaque()
10268 !arm_feature(&cpu->env, ARM_FEATURE_M)) { in define_one_arm_cp_reg_with_opaque()
10269 assert(r->cp >= 14 && r->cp <= 15); in define_one_arm_cp_reg_with_opaque()
10271 assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); in define_one_arm_cp_reg_with_opaque()
10275 assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); in define_one_arm_cp_reg_with_opaque()
10287 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
10289 switch (r->opc1) { in define_one_arm_cp_reg_with_opaque()
10316 /* broken reginfo with out-of-range opc1 */ in define_one_arm_cp_reg_with_opaque()
10320 assert((r->access & ~mask) == 0); in define_one_arm_cp_reg_with_opaque()
10327 if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { in define_one_arm_cp_reg_with_opaque()
10328 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
10329 assert((r->fieldoffset || in define_one_arm_cp_reg_with_opaque()
10330 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || in define_one_arm_cp_reg_with_opaque()
10331 r->readfn); in define_one_arm_cp_reg_with_opaque()
10333 if (r->access & PL3_W) { in define_one_arm_cp_reg_with_opaque()
10334 assert((r->fieldoffset || in define_one_arm_cp_reg_with_opaque()
10335 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || in define_one_arm_cp_reg_with_opaque()
10336 r->writefn); in define_one_arm_cp_reg_with_opaque()
10345 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { in define_one_arm_cp_reg_with_opaque()
10351 * (same for secure and non-secure world) or banked. in define_one_arm_cp_reg_with_opaque()
10355 switch (r->secure) { in define_one_arm_cp_reg_with_opaque()
10359 r->secure, crm, opc1, opc2, in define_one_arm_cp_reg_with_opaque()
10360 r->name); in define_one_arm_cp_reg_with_opaque()
10363 name = g_strdup_printf("%s_S", r->name); in define_one_arm_cp_reg_with_opaque()
10370 crm, opc1, opc2, r->name); in define_one_arm_cp_reg_with_opaque()
10377 * AArch64 registers get mapped to non-secure instance in define_one_arm_cp_reg_with_opaque()
10382 crm, opc1, opc2, r->name); in define_one_arm_cp_reg_with_opaque()
10405 * user-space cannot alter any values and dynamic values pertaining to
10416 if (m->is_glob) { in modify_arm_cp_regs_with_len()
10417 pat = g_pattern_spec_new(m->name); in modify_arm_cp_regs_with_len()
10422 if (pat && g_pattern_match_string(pat, r->name)) { in modify_arm_cp_regs_with_len()
10423 r->type = ARM_CP_CONST; in modify_arm_cp_regs_with_len()
10424 r->access = PL0U_R; in modify_arm_cp_regs_with_len()
10425 r->resetvalue = 0; in modify_arm_cp_regs_with_len()
10427 } else if (strcmp(r->name, m->name) == 0) { in modify_arm_cp_regs_with_len()
10428 r->type = ARM_CP_CONST; in modify_arm_cp_regs_with_len()
10429 r->access = PL0U_R; in modify_arm_cp_regs_with_len()
10430 r->resetvalue &= m->exported_bits; in modify_arm_cp_regs_with_len()
10431 r->resetvalue |= m->fixed_bits; in modify_arm_cp_regs_with_len()
10449 /* Helper coprocessor write function for write-ignore registers */ in arm_cp_write_ignore()
10454 /* Helper coprocessor write function for read-as-zero registers */ in arm_cp_read_zero()
10460 /* Helper coprocessor reset function for do-nothing-on-reset registers */ in arm_cp_reset_ignore()
10466 * Return true if it is not valid for us to switch to in bad_mode_switch()
10473 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || in bad_mode_switch()
10489 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) in bad_mode_switch()
10496 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && in bad_mode_switch()
10513 ZF = (env->ZF == 0); in cpsr_read()
10514 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | in cpsr_read()
10515 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in cpsr_read()
10516 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
10517 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
10518 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
10529 env->ZF = (~val) & CPSR_Z; in cpsr_write()
10530 env->NF = val; in cpsr_write()
10531 env->CF = (val >> 29) & 1; in cpsr_write()
10532 env->VF = (val << 3) & 0x80000000; in cpsr_write()
10535 env->QF = ((val & CPSR_Q) != 0); in cpsr_write()
10538 env->thumb = ((val & CPSR_T) != 0); in cpsr_write()
10541 env->condexec_bits &= ~3; in cpsr_write()
10542 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
10545 env->condexec_bits &= 3; in cpsr_write()
10546 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
10549 env->GE = (val >> 16) & 0xf; in cpsr_write()
10555 * whether non-secure software is allowed to change the CPSR_F and CPSR_A in cpsr_write()
10566 changed_daif = (env->daif ^ val) & mask; in cpsr_write()
10571 * abort exceptions from a non-secure state. in cpsr_write()
10573 if (!(env->cp15.scr_el3 & SCR_AW)) { in cpsr_write()
10576 "non-secure world with SCR.AW bit clear\n"); in cpsr_write()
10584 * exceptions from a non-secure state. in cpsr_write()
10586 if (!(env->cp15.scr_el3 & SCR_FW)) { in cpsr_write()
10589 "non-secure world with SCR.FW bit clear\n"); in cpsr_write()
10594 * Check whether non-maskable FIQ (NMFI) support is enabled. in cpsr_write()
10602 "(non-maskable FIQ [NMFI] support enabled)\n"); in cpsr_write()
10608 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
10609 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
10612 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { in cpsr_write()
10613 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { in cpsr_write()
10640 aarch32_mode_name(env->uncached_cpsr), in cpsr_write()
10647 aarch32_mode_name(env->uncached_cpsr), in cpsr_write()
10648 aarch32_mode_name(val), env->regs[15]); in cpsr_write()
10653 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); in cpsr_write()
10688 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()
10694 memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); in switch_mode()
10695 memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); in switch_mode()
10697 memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); in switch_mode()
10698 memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); in switch_mode()
10702 env->banked_r13[i] = env->regs[13]; in switch_mode()
10703 env->banked_spsr[i] = env->spsr; in switch_mode()
10706 env->regs[13] = env->banked_r13[i]; in switch_mode()
10707 env->spsr = env->banked_spsr[i]; in switch_mode()
10709 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; in switch_mode()
10710 env->regs[14] = env->banked_r14[r14_bank_number(mode)]; in switch_mode()
10716 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10718 * The below multi-dimensional table is used for looking up the target
10725 * | | | | | +--- Current EL
10726 * | | | | +------ Non-secure(0)/Secure(1)
10727 * | | | +--------- HCR mask override
10728 * | | +------------ SCR exec state control
10729 * | +--------------- SCR mask override
10730 * +------------------ 32-bit(0)/64-bit(1) EL3
10733 * 0-3 = EL0-EL3
10734 * -1 = Cannot occur
10748 * BIT IRQ IMO Non-secure Secure
10752 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10753 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10754 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10755 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10756 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10757 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10758 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10759 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10760 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10761 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10762 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10763 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10764 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10765 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10766 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10767 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10786 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); in arm_phys_excp_target_el()
10800 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); in arm_phys_excp_target_el()
10804 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); in arm_phys_excp_target_el()
10808 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); in arm_phys_excp_target_el()
10819 /* Perform a table-lookup for the target EL given the current state */ in arm_phys_excp_target_el()
10829 int idx = cs->exception_index; in arm_log_exception()
10870 idx, exc, cs->cpu_index); in arm_log_exception()
10882 uint32_t mode = env->uncached_cpsr & CPSR_M; in aarch64_sync_32_to_64()
10886 env->xregs[i] = env->regs[i]; in aarch64_sync_32_to_64()
10890 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. in aarch64_sync_32_to_64()
10895 env->xregs[i] = env->usr_regs[i - 8]; in aarch64_sync_32_to_64()
10899 env->xregs[i] = env->regs[i]; in aarch64_sync_32_to_64()
10904 * Registers x13-x23 are the various mode SP and FP registers. Registers in aarch64_sync_32_to_64()
10909 env->xregs[13] = env->regs[13]; in aarch64_sync_32_to_64()
10910 env->xregs[14] = env->regs[14]; in aarch64_sync_32_to_64()
10912 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; in aarch64_sync_32_to_64()
10915 env->xregs[14] = env->regs[14]; in aarch64_sync_32_to_64()
10917 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; in aarch64_sync_32_to_64()
10922 env->xregs[15] = env->regs[13]; in aarch64_sync_32_to_64()
10924 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; in aarch64_sync_32_to_64()
10928 env->xregs[16] = env->regs[14]; in aarch64_sync_32_to_64()
10929 env->xregs[17] = env->regs[13]; in aarch64_sync_32_to_64()
10931 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; in aarch64_sync_32_to_64()
10932 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; in aarch64_sync_32_to_64()
10936 env->xregs[18] = env->regs[14]; in aarch64_sync_32_to_64()
10937 env->xregs[19] = env->regs[13]; in aarch64_sync_32_to_64()
10939 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; in aarch64_sync_32_to_64()
10940 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; in aarch64_sync_32_to_64()
10944 env->xregs[20] = env->regs[14]; in aarch64_sync_32_to_64()
10945 env->xregs[21] = env->regs[13]; in aarch64_sync_32_to_64()
10947 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; in aarch64_sync_32_to_64()
10948 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; in aarch64_sync_32_to_64()
10952 env->xregs[22] = env->regs[14]; in aarch64_sync_32_to_64()
10953 env->xregs[23] = env->regs[13]; in aarch64_sync_32_to_64()
10955 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; in aarch64_sync_32_to_64()
10956 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; in aarch64_sync_32_to_64()
10960 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ in aarch64_sync_32_to_64()
10961 * mode, then we can copy from r8-r14. Otherwise, we copy from the in aarch64_sync_32_to_64()
10962 * FIQ bank for r8-r14. in aarch64_sync_32_to_64()
10966 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ in aarch64_sync_32_to_64()
10970 env->xregs[i] = env->fiq_regs[i - 24]; in aarch64_sync_32_to_64()
10972 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; in aarch64_sync_32_to_64()
10973 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; in aarch64_sync_32_to_64()
10976 env->pc = env->regs[15]; in aarch64_sync_32_to_64()
10987 uint32_t mode = env->uncached_cpsr & CPSR_M; in aarch64_sync_64_to_32()
10991 env->regs[i] = env->xregs[i]; in aarch64_sync_64_to_32()
10995 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. in aarch64_sync_64_to_32()
10996 * Otherwise, we copy x8-x12 into the banked user regs. in aarch64_sync_64_to_32()
11000 env->usr_regs[i - 8] = env->xregs[i]; in aarch64_sync_64_to_32()
11004 env->regs[i] = env->xregs[i]; in aarch64_sync_64_to_32()
11015 env->regs[13] = env->xregs[13]; in aarch64_sync_64_to_32()
11016 env->regs[14] = env->xregs[14]; in aarch64_sync_64_to_32()
11018 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; in aarch64_sync_64_to_32()
11025 env->regs[14] = env->xregs[14]; in aarch64_sync_64_to_32()
11027 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; in aarch64_sync_64_to_32()
11032 env->regs[13] = env->xregs[15]; in aarch64_sync_64_to_32()
11034 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; in aarch64_sync_64_to_32()
11038 env->regs[14] = env->xregs[16]; in aarch64_sync_64_to_32()
11039 env->regs[13] = env->xregs[17]; in aarch64_sync_64_to_32()
11041 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; in aarch64_sync_64_to_32()
11042 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; in aarch64_sync_64_to_32()
11046 env->regs[14] = env->xregs[18]; in aarch64_sync_64_to_32()
11047 env->regs[13] = env->xregs[19]; in aarch64_sync_64_to_32()
11049 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; in aarch64_sync_64_to_32()
11050 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; in aarch64_sync_64_to_32()
11054 env->regs[14] = env->xregs[20]; in aarch64_sync_64_to_32()
11055 env->regs[13] = env->xregs[21]; in aarch64_sync_64_to_32()
11057 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; in aarch64_sync_64_to_32()
11058 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; in aarch64_sync_64_to_32()
11062 env->regs[14] = env->xregs[22]; in aarch64_sync_64_to_32()
11063 env->regs[13] = env->xregs[23]; in aarch64_sync_64_to_32()
11065 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; in aarch64_sync_64_to_32()
11066 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; in aarch64_sync_64_to_32()
11070 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ in aarch64_sync_64_to_32()
11071 * mode, then we can copy to r8-r14. Otherwise, we copy to the in aarch64_sync_64_to_32()
11072 * FIQ bank for r8-r14. in aarch64_sync_64_to_32()
11076 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ in aarch64_sync_64_to_32()
11080 env->fiq_regs[i - 24] = env->xregs[i]; in aarch64_sync_64_to_32()
11082 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; in aarch64_sync_64_to_32()
11083 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; in aarch64_sync_64_to_32()
11086 env->regs[15] = env->pc; in aarch64_sync_64_to_32()
11100 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. in take_aarch32_exception()
11102 env->pstate &= ~PSTATE_SS; in take_aarch32_exception()
11103 env->spsr = cpsr_read(env); in take_aarch32_exception()
11105 env->condexec_bits = 0; in take_aarch32_exception()
11107 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; in take_aarch32_exception()
11113 env->uncached_cpsr &= ~CPSR_E; in take_aarch32_exception()
11114 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { in take_aarch32_exception()
11115 env->uncached_cpsr |= CPSR_E; in take_aarch32_exception()
11118 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); in take_aarch32_exception()
11119 env->daif |= mask; in take_aarch32_exception()
11122 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { in take_aarch32_exception()
11123 env->uncached_cpsr |= CPSR_SSBS; in take_aarch32_exception()
11125 env->uncached_cpsr &= ~CPSR_SSBS; in take_aarch32_exception()
11130 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; in take_aarch32_exception()
11131 env->elr_el[2] = env->regs[15]; in take_aarch32_exception()
11138 /* ... the target is EL3, from non-secure state. */ in take_aarch32_exception()
11139 env->uncached_cpsr &= ~CPSR_PAN; in take_aarch32_exception()
11146 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { in take_aarch32_exception()
11147 env->uncached_cpsr |= CPSR_PAN; in take_aarch32_exception()
11157 env->thumb = in take_aarch32_exception()
11160 env->regs[14] = env->regs[15] + offset; in take_aarch32_exception()
11162 env->regs[15] = newpc; in take_aarch32_exception()
11184 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt_aarch32_hyp()
11186 switch (cs->exception_index) { in arm_cpu_do_interrupt_aarch32_hyp()
11196 env->cp15.ifar_s = env->exception.vaddress; in arm_cpu_do_interrupt_aarch32_hyp()
11198 (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32_hyp()
11202 env->cp15.dfar_s = env->exception.vaddress; in arm_cpu_do_interrupt_aarch32_hyp()
11204 (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32_hyp()
11220 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_cpu_do_interrupt_aarch32_hyp()
11223 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { in arm_cpu_do_interrupt_aarch32_hyp()
11226 * QEMU syndrome values are v8-style. v7 has the IL bit in arm_cpu_do_interrupt_aarch32_hyp()
11227 * UNK/SBZP for "field not valid" cases, where v8 uses RES1. in arm_cpu_do_interrupt_aarch32_hyp()
11230 if (cs->exception_index == EXCP_PREFETCH_ABORT || in arm_cpu_do_interrupt_aarch32_hyp()
11231 (cs->exception_index == EXCP_DATA_ABORT && in arm_cpu_do_interrupt_aarch32_hyp()
11232 !(env->exception.syndrome & ARM_EL_ISV)) || in arm_cpu_do_interrupt_aarch32_hyp()
11233 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { in arm_cpu_do_interrupt_aarch32_hyp()
11234 env->exception.syndrome &= ~ARM_EL_IL; in arm_cpu_do_interrupt_aarch32_hyp()
11237 env->cp15.esr_el[2] = env->exception.syndrome; in arm_cpu_do_interrupt_aarch32_hyp()
11245 if (!(env->cp15.scr_el3 & SCR_EA)) { in arm_cpu_do_interrupt_aarch32_hyp()
11248 if (!(env->cp15.scr_el3 & SCR_IRQ)) { in arm_cpu_do_interrupt_aarch32_hyp()
11251 if (!(env->cp15.scr_el3 & SCR_FIQ)) { in arm_cpu_do_interrupt_aarch32_hyp()
11255 addr += env->cp15.hvbar; in arm_cpu_do_interrupt_aarch32_hyp()
11263 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt_aarch32()
11271 switch (syn_get_ec(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch32()
11292 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); in arm_cpu_do_interrupt_aarch32()
11295 if (env->exception.target_el == 2) { in arm_cpu_do_interrupt_aarch32()
11297 switch (syn_get_ec(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch32()
11302 env->exception.syndrome = syn_insn_abort(arm_current_el(env) == 2, in arm_cpu_do_interrupt_aarch32()
11306 env->exception.syndrome = syn_set_ec(env->exception.syndrome, in arm_cpu_do_interrupt_aarch32()
11310 env->exception.syndrome = syn_set_ec(env->exception.syndrome, in arm_cpu_do_interrupt_aarch32()
11318 switch (cs->exception_index) { in arm_cpu_do_interrupt_aarch32()
11323 if (env->thumb) { in arm_cpu_do_interrupt_aarch32()
11339 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
11340 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
11342 env->exception.fsr, (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
11349 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
11350 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
11352 env->exception.fsr, in arm_cpu_do_interrupt_aarch32()
11353 (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
11365 if (env->cp15.scr_el3 & SCR_IRQ) { in arm_cpu_do_interrupt_aarch32()
11376 if (env->cp15.scr_el3 & SCR_FIQ) { in arm_cpu_do_interrupt_aarch32()
11406 env->exception.fsr = arm_fi_to_lfsc(&fi); in arm_cpu_do_interrupt_aarch32()
11408 env->exception.fsr = arm_fi_to_sfsc(&fi); in arm_cpu_do_interrupt_aarch32()
11410 env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; in arm_cpu_do_interrupt_aarch32()
11411 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
11413 env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
11428 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_cpu_do_interrupt_aarch32()
11433 addr += env->cp15.mvbar; in arm_cpu_do_interrupt_aarch32()
11435 /* High vectors. When enabled, base address cannot be remapped. */ in arm_cpu_do_interrupt_aarch32()
11441 * This register is only followed in non-monitor mode, and is banked. in arm_cpu_do_interrupt_aarch32()
11442 * Note: only bits 31:5 are valid. in arm_cpu_do_interrupt_aarch32()
11447 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_cpu_do_interrupt_aarch32()
11448 env->cp15.scr_el3 &= ~SCR_NS; in arm_cpu_do_interrupt_aarch32()
11461 int mode = env->uncached_cpsr & CPSR_M; in aarch64_regnum()
11524 ret |= env->pstate & PSTATE_SS; in cpsr_read_for_spsr_elx()
11558 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt_aarch64()
11559 unsigned int new_el = env->exception.target_el; in arm_cpu_do_interrupt_aarch64()
11560 target_ulong addr = env->cp15.vbar_el[new_el]; in arm_cpu_do_interrupt_aarch64()
11584 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; in arm_cpu_do_interrupt_aarch64()
11609 switch (cs->exception_index) { in arm_cpu_do_interrupt_aarch64()
11612 env->cp15.mfar_el3); in arm_cpu_do_interrupt_aarch64()
11620 if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && in arm_cpu_do_interrupt_aarch64()
11621 syndrome_is_sync_extabt(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch64()
11624 env->cp15.far_el[new_el] = env->exception.vaddress; in arm_cpu_do_interrupt_aarch64()
11626 env->cp15.far_el[new_el]); in arm_cpu_do_interrupt_aarch64()
11634 switch (syn_get_ec(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch64()
11639 * is taken to AArch32 Hyp mode. Mask them out to get a valid in arm_cpu_do_interrupt_aarch64()
11642 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); in arm_cpu_do_interrupt_aarch64()
11651 * number. Notice that we read a 4-bit AArch32 register number and in arm_cpu_do_interrupt_aarch64()
11652 * write back a 5-bit AArch64 one. in arm_cpu_do_interrupt_aarch64()
11654 rt = extract32(env->exception.syndrome, 5, 4); in arm_cpu_do_interrupt_aarch64()
11656 env->exception.syndrome = deposit32(env->exception.syndrome, in arm_cpu_do_interrupt_aarch64()
11662 rt = extract32(env->exception.syndrome, 5, 4); in arm_cpu_do_interrupt_aarch64()
11664 env->exception.syndrome = deposit32(env->exception.syndrome, in arm_cpu_do_interrupt_aarch64()
11666 rt = extract32(env->exception.syndrome, 10, 4); in arm_cpu_do_interrupt_aarch64()
11668 env->exception.syndrome = deposit32(env->exception.syndrome, in arm_cpu_do_interrupt_aarch64()
11672 env->cp15.esr_el[new_el] = env->exception.syndrome; in arm_cpu_do_interrupt_aarch64()
11688 env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); in arm_cpu_do_interrupt_aarch64()
11689 env->cp15.esr_el[new_el] = env->exception.syndrome; in arm_cpu_do_interrupt_aarch64()
11692 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_cpu_do_interrupt_aarch64()
11698 env->elr_el[new_el] = env->pc; in arm_cpu_do_interrupt_aarch64()
11708 * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM) in arm_cpu_do_interrupt_aarch64()
11715 env->elr_el[new_el] = env->regs[15]; in arm_cpu_do_interrupt_aarch64()
11719 env->condexec_bits = 0; in arm_cpu_do_interrupt_aarch64()
11721 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; in arm_cpu_do_interrupt_aarch64()
11725 env->elr_el[new_el]); in arm_cpu_do_interrupt_aarch64()
11741 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { in arm_cpu_do_interrupt_aarch64()
11752 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { in arm_cpu_do_interrupt_aarch64()
11760 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) { in arm_cpu_do_interrupt_aarch64()
11768 env->aarch64 = true; in arm_cpu_do_interrupt_aarch64()
11775 env->pc = addr; in arm_cpu_do_interrupt_aarch64()
11778 new_el, env->pc, pstate_read(env)); in arm_cpu_do_interrupt_aarch64()
11792 CPUARMState *env = &cpu->env; in tcg_handle_semihosting()
11797 env->xregs[0]); in tcg_handle_semihosting()
11799 env->pc += 4; in tcg_handle_semihosting()
11803 env->regs[0]); in tcg_handle_semihosting()
11805 env->regs[15] += env->thumb ? 2 : 4; in tcg_handle_semihosting()
11813 * to the AArch64-entry or AArch32-entry function depending on the
11817 * and KVM to re-inject guest debug exceptions, and to
11818 * inject a Synchronous-External-Abort.
11823 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt()
11824 unsigned int new_el = env->exception.target_el; in arm_cpu_do_interrupt()
11832 && !excp_is_internal(cs->exception_index)) { in arm_cpu_do_interrupt()
11834 syn_get_ec(env->exception.syndrome), in arm_cpu_do_interrupt()
11835 env->exception.syndrome); in arm_cpu_do_interrupt()
11838 if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { in arm_cpu_do_interrupt()
11850 if (cs->exception_index == EXCP_SEMIHOST) { in arm_cpu_do_interrupt()
11859 * cs->interrupt_request. in arm_cpu_do_interrupt()
11865 assert(!excp_is_internal(cs->exception_index)); in arm_cpu_do_interrupt()
11875 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; in arm_cpu_do_interrupt()
11897 return env->cp15.sctlr_el[el]; in arm_sctlr()
12050 * determining if address tagging is enabled. in aa64_va_parameters()
12082 max_tsz = 48 - (gran == Gran64K); in aa64_va_parameters()
12118 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements in aa64_va_parameters()
12119 * are loosened: a configured IPA of 40 bits is permitted even if in aa64_va_parameters()
12120 * the implemented PA is less than that (and so a 40 bit IPA would in aa64_va_parameters()
12167 /* Perform 16-bit signed saturating addition. */
12183 /* Perform 8-bit signed saturating addition. */
12199 /* Perform 16-bit signed saturating subtraction. */
12204 res = a - b; in sub16_sat()
12215 /* Perform 8-bit signed saturating subtraction. */
12220 res = a - b; in sub8_sat()
12253 return a - b; in sub16_usat()
12272 return a - b; in sub8_usat()
12305 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12307 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12332 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12340 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12355 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12359 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12368 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12372 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12380 return a - b; in do_usad()
12382 return b - a; in do_usad()
12444 * Return the exception level to which FP-disabled exceptions should
12445 * be taken, or 0 if FP is enabled.
12462 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { in fp_exception_el()
12466 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { in fp_exception_el()
12467 if (!extract32(env->v7m.nsacr, 10, 1)) { in fp_exception_el()
12486 int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); in fp_exception_el()
12509 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode in fp_exception_el()
12510 * to control non-secure access to the FPU. It doesn't have any in fp_exception_el()
12515 if (!extract32(env->cp15.nsacr, 10, 1)) { in fp_exception_el()
12527 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { in fp_exception_el()
12538 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { in fp_exception_el()
12545 if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { in fp_exception_el()
12593 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); in arm_mmu_idx_el()
12596 /* See ARM pseudo-function ELIsInHost. */ in arm_mmu_idx_el()
12654 * NOTE: if you change this logic, the "recalculate s->mve_no_pred" in mve_no_pred()
12657 * We do not include the effect of the ECI bits here -- they are in mve_no_pred()
12665 if (env->v7m.vpr) { in mve_no_pred()
12668 if (env->v7m.ltpsize < 4) { in mve_no_pred()
12680 flags = env->hflags; in cpu_get_tb_cpu_state()
12683 *pc = env->pc; in cpu_get_tb_cpu_state()
12685 DP_TBFLAG_A64(flags, BTYPE, env->btype); in cpu_get_tb_cpu_state()
12688 *pc = env->regs[15]; in cpu_get_tb_cpu_state()
12692 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in cpu_get_tb_cpu_state()
12693 != env->v7m.secure) { in cpu_get_tb_cpu_state()
12697 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && in cpu_get_tb_cpu_state()
12698 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || in cpu_get_tb_cpu_state()
12699 (env->v7m.secure && in cpu_get_tb_cpu_state()
12700 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { in cpu_get_tb_cpu_state()
12709 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in cpu_get_tb_cpu_state()
12710 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { in cpu_get_tb_cpu_state()
12720 * Note that VECLEN+VECSTRIDE are RES0 for M-profile. in cpu_get_tb_cpu_state()
12723 DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); in cpu_get_tb_cpu_state()
12725 DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); in cpu_get_tb_cpu_state()
12726 DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); in cpu_get_tb_cpu_state()
12728 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { in cpu_get_tb_cpu_state()
12733 DP_TBFLAG_AM32(flags, THUMB, env->thumb); in cpu_get_tb_cpu_state()
12734 DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); in cpu_get_tb_cpu_state()
12742 * 1 0 Active-pending in cpu_get_tb_cpu_state()
12743 * 1 1 Active-not-pending in cpu_get_tb_cpu_state()
12746 if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { in cpu_get_tb_cpu_state()
12756 * The manual says that when SVE is enabled and VQ is widened the
12759 * SVE is enabled and VQ is narrowed we are also allowed to zero
12775 assert(vq <= env_archcpu(env)->sve_max_vq); in aarch64_sve_narrow_vq()
12779 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); in aarch64_sve_narrow_vq()
12785 pmask = ~(-1ULL << (16 * (vq & 3))); in aarch64_sve_narrow_vq()
12789 env->vfp.pregs[i].p[j] &= pmask; in aarch64_sve_narrow_vq()
12836 * returning to, AArch32 state when PSTATE.SM is enabled. in aarch64_sve_change_el()
12838 sm = FIELD_EX64(env->svcr, SVCR, SM); in aarch64_sve_change_el()
12850 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). in aarch64_sve_change_el()
12851 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition in aarch64_sve_change_el()
12852 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that in aarch64_sve_change_el()
12854 * vq0->vq0 transition between EL0->EL1. in aarch64_sve_change_el()
12875 return arm_secure_to_space(env->v7m.secure); in arm_security_space()
12880 * defined, in which case QEMU defaults to non-secure. in arm_security_space()
12888 if (extract32(env->pstate, 2, 2) == 3) { in arm_security_space()
12896 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_security_space()
12910 * defined, in which case QEMU defaults to non-secure. in arm_security_space_below_el3()
12921 if (!(env->cp15.scr_el3 & SCR_NS)) { in arm_security_space_below_el3()
12923 } else if (env->cp15.scr_el3 & SCR_NSE) { in arm_security_space_below_el3()