Lines Matching +full:migration +full:- +full:compat +full:- +full:aarch64
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
80 /* ARM-specific interrupt pending bits. */
89 /* The usual mapping for an AArch64 system register to its AArch32
103 /* ARM-specific extra insn start words:
114 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
149 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
150 * For 64-bit, this is a 2048-bit SVE register.
153 * differs between AArch64 and AArch32.
160 * In AArch64:
222 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
224 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
225 * DAIF (exception masks) are kept in env->daif
226 * BTYPE is kept in env->btype
227 * SM and ZA are kept in env->svcr
228 * all other bits are stored in their correct places in env->pstate
231 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ member
248 /* These hold r8-r12. */
264 uint64_t elr_el[4]; /* AArch64 exception link regs */
265 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
293 uint32_t nsacr; /* Non-secure access control register. */
464 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
465 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
466 uint32_t c15_threadid; /* TI debugger thread-ID. */
484 * architecturally-correct value is being read/set.
511 * Fine-Grained Trap registers. We store these as arrays so the
532 * of the Secure and Non-Secure states. (If the CPU doesn't support
535 * and the non-active SP for the current security state in
575 * code which raises an exception must set cs->exception_index and
577 * will then set the guest-visible registers as part of the exception
581 uint32_t syndrome; /* AArch64 format syndrome register */
602 /* Thumb-2 EE state. */
638 * fp_status_fp16: used for half-precision calculations
640 * standard_fp_status_fp16 : used for half-precision
643 * Half-precision operations are governed by a separate
644 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
647 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
648 * round-to-nearest and is used by any operations (generally
667 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
668 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
674 * Contains the 'val' for the second 64-bit register of LDXP, which comes
675 * from the higher address, not the high part of a complete 128-bit value.
678 * semantics of these fields are baked into the migration format.
702 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
704 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
788 env->features |= 1ULL << feature; in set_feature()
793 env->features &= ~(1ULL << feature); in unset_feature()
820 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
846 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
857 /* These are used only for migration: incoming data arrives in
873 * Timer used by the PMU. Its state is restored after migration by
874 * pmu_op_finish() - it does not need other handling during migration
921 /* CPU has M-profile DSP extension */
936 * 0 - disabled, 1 - smc, 2 - hvc
942 /* For v8M, initial value of the Non-secure VTOR */
973 /* QOM property to indicate we should use the back-compat CNTFRQ default */
981 /* The instance init functions for implementation-specific subclasses
982 * set these fields to specify the implementation-dependent values of
983 * various constant registers and reset values of non-constant
988 * is used for reset values of non-constant registers; no reset_
994 * you need to also update the 32-bit and 64-bit versions of the
1082 * big-endian mode). This setting isn't used directly: instead it modifies
1093 /* Used to synchronize KVM and QEMU in-kernel device levels */
1196 * lower exception level. This function does that post-reset CPU setup,
1217 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1218 * The byte at offset i from the start of the in-memory representation contains
1221 * matches QEMU's representation, which is to use an array of host-endian
1223 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1261 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1271 return env->aarch64; in is_a64()
1279 * they are enabled) and the guest-visible values. These two calls must
1315 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1316 #define SCTLR_SA (1U << 3) /* AArch64 only */
1318 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1319 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1329 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1332 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1334 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1337 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1339 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1341 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1351 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1353 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1355 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1357 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1359 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1362 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1364 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1366 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1368 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1370 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1371 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1375 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1376 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1377 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1378 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1379 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1380 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1381 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1382 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1447 * Only these are valid when in AArch64 mode; in
1448 * AArch32 mode SPSRs are basically CPSR-format.
1473 /* Mode values for AArch64 */
1501 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1509 ZF = (env->ZF == 0); in pstate_read()
1510 return (env->NF & 0x80000000) | (ZF << 30) in pstate_read()
1511 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) in pstate_read()
1512 | env->pstate | env->daif | (env->btype << 10); in pstate_read()
1517 env->ZF = (~val) & PSTATE_Z; in pstate_write()
1518 env->NF = val; in pstate_write()
1519 env->CF = (val >> 29) & 1; in pstate_write()
1520 env->VF = (val << 3) & 0x80000000; in pstate_write()
1521 env->daif = val & PSTATE_DAIF; in pstate_write()
1522 env->btype = (val >> 10) & 3; in pstate_write()
1523 env->pstate = val & ~CACHED_PSTATE_BITS; in pstate_write()
1538 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1550 ZF = (env->ZF == 0); in xpsr_read()
1551 return (env->NF & 0x80000000) | (ZF << 30) in xpsr_read()
1552 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in xpsr_read()
1553 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1554 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1555 | (env->GE << 16) in xpsr_read()
1556 | env->v7m.exception; in xpsr_read()
1559 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1563 env->ZF = (~val) & XPSR_Z; in xpsr_write()
1564 env->NF = val; in xpsr_write()
1565 env->CF = (val >> 29) & 1; in xpsr_write()
1566 env->VF = (val << 3) & 0x80000000; in xpsr_write()
1569 env->QF = ((val & XPSR_Q) != 0); in xpsr_write()
1572 env->GE = (val & XPSR_GE) >> 16; in xpsr_write()
1576 env->thumb = ((val & XPSR_T) != 0); in xpsr_write()
1579 env->condexec_bits &= ~3; in xpsr_write()
1580 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1583 env->condexec_bits &= 3; in xpsr_write()
1584 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1718 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1719 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1722 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1724 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1726 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1762 * vfp_get_fpsr: read the AArch64 FPSR
1765 * Return the current AArch64 FPSR value
1770 * vfp_get_fpcr: read the AArch64 FPCR
1773 * Return the current AArch64 FPCR value
1778 * vfp_set_fpsr: write the AArch64 FPSR
1785 * vfp_set_fpcr: write the AArch64 FPCR
1812 /* These ones are M-profile only */
1819 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1930 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1955 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
2367 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2368 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2369 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2370 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2371 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2372 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2392 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2395 * HWCAP bit, remember to update the feature-bit-to-hwcap
2396 * mapping in linux-user/elfload.c:get_elf_hwcap().
2412 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2420 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2428 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2449 return (env->features & (1ULL << feature)) != 0; in arm_feature()
2467 /* Return true if @space is secure, in the pre-v9 sense. */
2473 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2503 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2508 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { in arm_is_el3_or_mon()
2509 /* CPU currently in AArch64 state and EL3 */ in arm_is_el3_or_mon()
2512 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
2540 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2548 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled_secstate()
2604 /* Return true if the specified exception level is running in AArch64 state. */
2622 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { in arm_el_is_aa64()
2623 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); in arm_el_is_aa64()
2631 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); in arm_el_is_aa64()
2638 * access the secure or non-secure bank of a cp register. When EL3 is
2639 * operating in AArch32 state, the NS-bit determines whether the secure
2640 * instance of a cp register should be used. When EL3 is AArch64 (or if
2642 * accesses are to the non-secure version.
2648 !(env->cp15.scr_el3 & SCR_NS)); in access_secure_reg()
2655 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2660 (_env)->cp15._regname##_s = (_val); \
2662 (_env)->cp15._regname##_ns = (_val); \
2698 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2708 !(env->v7m.control[env->v7m.secure] & 1); in arm_current_el()
2712 return extract32(env->pstate, 2, 2); in arm_current_el()
2715 switch (env->uncached_cpsr & 0x1f) { in arm_current_el()
2724 /* If EL3 is 32-bit then all secure privileged modes run in in arm_current_el()
2741 * from incoming migration state.
2745 * Note that we do not stop early on failure -- we will attempt
2758 * KVM or for outbound migration.
2762 * values in the list if the previous list->cpustate sync actually
2768 * Note that we do not stop early on failure -- we will attempt
2778 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2782 * If EL3 is 64-bit:
2786 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2795 * If EL3 is 32-bit:
2804 * because they may differ in access permissions even if the VA->PA map is
2806 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2813 * which can be slow-pathed and always do a page table walk.
2825 * 7. we fold together most secure and non-secure regimes for A-profile,
2826 * because there are no banked system registers for aarch64, so the
2827 * process of switching between secure and non-secure is
2852 * EL2 for cores like the Cortex-R52).
2867 * are not quite the same -- different CPU types (most notably M profile
2902 * A-profile.
2924 /* TLBs with 1-1 mapping to the physical address spaces. */
2939 * M-profile.
2952 * Bit macros for the core-mmu-index values for each index,
3008 return idx - ARMMMUIdx_Phys_S; in arm_phys_to_space()
3016 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; in arm_v7m_csselr_razwi()
3022 /* We need not implement SCTLR.ITD in user-mode emulation, so in arm_sctlr_b()
3023 * let linux-user ignore the fact that it conflicts with SCTLR_B. in arm_sctlr_b()
3024 * This lets people run BE32 binaries with "-cpu any". in arm_sctlr_b()
3029 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
3040 * architecture (as word-invariant big-endianness), where loads in arm_cpu_data_is_big_endian_a32()
3045 * In user mode, however, we model BE32 as byte-invariant in arm_cpu_data_is_big_endian_a32()
3046 * big-endianness (because user-only code cannot tell the in arm_cpu_data_is_big_endian_a32()
3055 return env->uncached_cpsr & CPSR_E; in arm_cpu_data_is_big_endian_a32()
3063 /* Return true if the processor is in big-endian mode. */
3075 #include "exec/cpu-all.h"
3078 * We have more than 32-bits worth of state per TB, so we split the data
3079 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3086 * address size, flags2 always has 64-bits for A64, and a minimum of
3087 * 32-bits for A32 and M32.
3089 * The bits for 32-bit A-profile and M-profile partially overlap:
3092 * +-------------+----------+----------------+
3094 * | TBFLAG_AM32 | +-----+----------+
3096 * +-------------+----------------+----------+
3099 * Unless otherwise noted, these bits are cached in env->hflags.
3106 /* Target EL if we take a floating-point-disabled exception */
3115 * Bit usage when in AArch32 state, both A- and M-profile.
3121 * Bit usage when in AArch32 state, for A-profile only.
3148 * Bit usage when in AArch32 state, for M-profile only.
3152 /* Whether we should generate stack-limit checks */
3166 * Bit usage when in AArch64 state
3195 /* Set if FEAT_NV2 RAM accesses are big-endian */
3224 * Return the VL cached within env->hflags, in units of quadwords.
3228 return EX_TBFLAG_A64(env->hflags, VL) + 1; in sve_vq()
3235 * Return the SVL cached within env->hflags, in units of quadwords.
3239 return EX_TBFLAG_A64(env->hflags, SVL) + 1; in sme_vq()
3247 * would also end up as a mixed-endian mode with BE code, LE data. in bswap_code()
3298 * Note that if a pre-change hook is called, any registered post-change hooks
3311 * if pre-change hooks have been.
3324 * Return a pointer to the Dn register within env in 32-bit mode.
3328 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg()
3333 * Return a pointer to the Qn register within env in 32-bit mode.
3337 return &env->vfp.zregs[regno].d[0]; in aa32_vfp_qreg()
3342 * Return a pointer to the Qn register within env in 64-bit mode.
3346 return &env->vfp.zregs[regno].d[0]; in aa64_vfp_qreg()
3349 /* Shared between translate-sve.c and sve_helper.c. */
3353 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3379 * include/exec/cpu_ldst.h, and not some place linux-user specific.
3384 if (env->tagged_addr_enable) { in cpu_untagged_addr()