Lines Matching +full:low +full:- +full:profile
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-common.h"
28 #include "exec/cpu-defs.h"
29 #include "exec/cpu-interrupt.h"
31 #include "exec/page-protection.h"
32 #include "qapi/qapi-types-common.h"
35 #include "target/arm/cpu-sysregs.h"
79 /* ARM-specific interrupt pending bits. */
107 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
142 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
143 * For 64-bit, this is a 2048-bit SVE register.
198 * FPST_A32_F16: used for AArch32 half-precision calculations
199 * FPST_A64_F16: used for AArch64 half-precision calculations
201 * FPST_STD_F16: used for half-precision
209 * for half-precision
211 * ZA_F16: likewise for half-precision.
213 * Half-precision operations are governed by a separate
214 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
217 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
218 * round-to-nearest and is used by any operations (generally
233 * default-NaN and do not generate fp exceptions, which means that they
274 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
276 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
277 * DAIF (exception masks) are kept in env->daif
278 * BTYPE is kept in env->btype
279 * SM and ZA are kept in env->svcr
280 * all other bits are stored in their correct places in env->pstate
300 /* These hold r8-r12. */
345 uint32_t nsacr; /* Non-secure access control register. */
516 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
517 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
518 uint32_t c15_threadid; /* TI debugger thread-ID. */
536 * architecturally-correct value is being read/set.
563 * Fine-Grained Trap registers. We store these as arrays so the
582 /* M profile has up to 4 stack pointers:
584 * of the Secure and Non-Secure states. (If the CPU doesn't support
587 * and the non-active SP for the current security state in
627 * code which raises an exception must set cs->exception_index and
629 * will then set the guest-visible registers as part of the exception
654 /* Thumb-2 EE state. */
685 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
686 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
692 * Contains the 'val' for the second 64-bit register of LDXP, which comes
693 * from the higher address, not the high part of a complete 128-bit value.
695 * as the low and high halves of a 128 bit data value, but the current
719 /* SME2 ZT0 -- 512 bit array, with data ordered like ARMVectorReg. */
723 * SME ZA storage -- 256 x 256 byte array, with bytes in host
726 * significant bytes of env->za_state.za[N].
810 env->features |= 1ULL << feature; in set_feature()
815 env->features &= ~(1ULL << feature); in unset_feature()
842 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
858 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
860 i_->idregs[REG ## _EL1_IDX] = regval; \
866 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
868 i_->idregs[REG ## _EL1_IDX] = regval; \
874 FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
880 FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
886 FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
892 i_->idregs[REG ## _EL1_IDX] = VALUE; \
898 i_->idregs[REG ## _EL1_IDX]; \
943 * pmu_op_finish() - it does not need other handling during migration
990 /* CPU has M-profile DSP extension */
1005 * 0 - disabled, 1 - smc, 2 - hvc
1011 /* For v8M, initial value of the Non-secure VTOR */
1040 /* QOM property to indicate we should use the back-compat CNTFRQ default */
1043 /* QOM property to indicate we should use the back-compat QARMA5 default */
1051 /* The instance init functions for implementation-specific subclasses
1052 * set these fields to specify the implementation-dependent values of
1053 * various constant registers and reset values of non-constant
1058 * is used for reset values of non-constant registers; no reset_
1064 * you need to also update the 32-bit and 64-bit versions of the
1105 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
1107 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
1119 * big-endian mode). This setting isn't used directly: instead it modifies
1130 /* Used to synchronize KVM and QEMU in-kernel device levels */
1229 * lower exception level. This function does that post-reset CPU setup,
1249 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1250 * The byte at offset i from the start of the in-memory representation contains
1253 * matches QEMU's representation, which is to use an array of host-endian
1255 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1286 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1296 return env->aarch64; in is_a64()
1304 * they are enabled) and the guest-visible values. These two calls must
1340 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1343 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1357 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1359 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1378 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1380 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1382 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1391 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1393 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1400 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1401 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1402 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1403 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1404 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1405 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1406 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1455 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1473 * AArch32 mode SPSRs are basically CPSR-format.
1527 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1535 ZF = (env->ZF == 0); in pstate_read()
1536 return (env->NF & 0x80000000) | (ZF << 30) in pstate_read()
1537 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) in pstate_read()
1538 | env->pstate | env->daif | (env->btype << 10); in pstate_read()
1543 env->ZF = (~val) & PSTATE_Z; in pstate_write()
1544 env->NF = val; in pstate_write()
1545 env->CF = (val >> 29) & 1; in pstate_write()
1546 env->VF = (val << 3) & 0x80000000; in pstate_write()
1547 env->daif = val & PSTATE_DAIF; in pstate_write()
1548 env->btype = (val >> 10) & 3; in pstate_write()
1549 env->pstate = val & ~CACHED_PSTATE_BITS; in pstate_write()
1564 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1576 ZF = (env->ZF == 0); in xpsr_read()
1577 return (env->NF & 0x80000000) | (ZF << 30) in xpsr_read()
1578 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in xpsr_read()
1579 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1580 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1581 | (env->GE << 16) in xpsr_read()
1582 | env->v7m.exception; in xpsr_read()
1585 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1589 env->ZF = (~val) & XPSR_Z; in xpsr_write()
1590 env->NF = val; in xpsr_write()
1591 env->CF = (val >> 29) & 1; in xpsr_write()
1592 env->VF = (val << 3) & 0x80000000; in xpsr_write()
1595 env->QF = ((val & XPSR_Q) != 0); in xpsr_write()
1598 env->GE = (val & XPSR_GE) >> 16; in xpsr_write()
1602 env->thumb = ((val & XPSR_T) != 0); in xpsr_write()
1605 env->condexec_bits &= ~3; in xpsr_write()
1606 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1609 env->condexec_bits &= 3; in xpsr_write()
1610 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1747 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1748 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1751 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1753 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1755 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1841 /* These ones are M-profile only */
1848 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1959 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1984 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
2397 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2398 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2399 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2400 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2401 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2402 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2422 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2425 * HWCAP bit, remember to update the feature-bit-to-hwcap
2426 * mapping in linux-user/elfload.c:get_elf_hwcap().
2438 ARM_FEATURE_M, /* Microcontroller profile. */
2442 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2450 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2458 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2464 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2465 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2466 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2479 return (env->features & (1ULL << feature)) != 0; in arm_feature()
2486 * The ordering of the enumeration corresponds to the low 2 bits
2497 /* Return true if @space is secure, in the pre-v9 sense. */
2503 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2538 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { in arm_is_el3_or_mon()
2542 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
2578 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled_secstate()
2636 * access the secure or non-secure bank of a cp register. When EL3 is
2637 * operating in AArch32 state, the NS-bit determines whether the secure
2640 * accesses are to the non-secure version.
2662 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2676 * Note that we do not stop early on failure -- we will attempt
2693 * values in the list if the previous list->cpustate sync actually
2699 * Note that we do not stop early on failure -- we will attempt
2709 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2713 * If EL3 is 64-bit:
2717 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2726 * If EL3 is 32-bit:
2735 * because they may differ in access permissions even if the VA->PA map is
2737 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2744 * which can be slow-pathed and always do a page table walk.
2756 * 7. we fold together most secure and non-secure regimes for A-profile,
2758 * process of switching between secure and non-secure is
2781 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2782 * as A profile. They only need to distinguish EL0 and EL1 (and
2783 * EL2 for cores like the Cortex-R52).
2785 * M profile CPUs are rather different as they do not have a true MMU.
2798 * are not quite the same -- different CPU types (most notably M profile
2799 * vs A/R profile) would like to use MMU indexes with different semantics,
2801 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2802 * modes + total number of M profile MMU modes". The lower bits of
2815 * For M profile we arrange them to have a bit for priv, a bit for negpri
2818 #define ARM_MMU_IDX_A 0x10 /* A profile */
2820 #define ARM_MMU_IDX_M 0x40 /* M profile */
2822 /* Meanings of the bits for M profile mmu idx values */
2833 * A-profile.
2855 /* TLBs with 1-1 mapping to the physical address spaces. */
2870 * M-profile.
2883 * Bit macros for the core-mmu-index values for each index,
2939 return idx - ARMMMUIdx_Phys_S; in arm_phys_to_space()
2947 return (GET_IDREG(&cpu->isar, CLIDR) & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; in arm_v7m_csselr_razwi()
2953 /* We need not implement SCTLR.ITD in user-mode emulation, so in arm_sctlr_b()
2954 * let linux-user ignore the fact that it conflicts with SCTLR_B. in arm_sctlr_b()
2955 * This lets people run BE32 binaries with "-cpu any". in arm_sctlr_b()
2960 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
2966 * We have more than 32-bits worth of state per TB, so we split the data
2967 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
2973 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32.
2975 * The bits for 32-bit A-profile and M-profile partially overlap:
2978 * +-------------+----------+----------------+
2980 * | TBFLAG_AM32 | +-----+----------+
2982 * +-------------+----------------+----------+
2985 * Unless otherwise noted, these bits are cached in env->hflags.
2992 /* Target EL if we take a floating-point-disabled exception */
3001 * Bit usage when in AArch32 state, both A- and M-profile.
3007 * Bit usage when in AArch32 state, for A-profile only.
3034 * Bit usage when in AArch32 state, for M-profile only.
3038 /* Whether we should generate stack-limit checks */
3081 /* Set if FEAT_NV2 RAM accesses are big-endian */
3113 * Return the VL cached within env->hflags, in units of quadwords.
3117 return EX_TBFLAG_A64(env->hflags, VL) + 1; in sve_vq()
3124 * Return the SVL cached within env->hflags, in units of quadwords.
3128 return EX_TBFLAG_A64(env->hflags, SVL) + 1; in sme_vq()
3136 * would also end up as a mixed-endian mode with BE code, LE data. in bswap_code()
3177 * Note that if a pre-change hook is called, any registered post-change hooks
3190 * if pre-change hooks have been.
3203 * Return a pointer to the Dn register within env in 32-bit mode.
3207 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg()
3212 * Return a pointer to the Qn register within env in 32-bit mode.
3216 return &env->vfp.zregs[regno].d[0]; in aa32_vfp_qreg()
3221 * Return a pointer to the Qn register within env in 64-bit mode.
3225 return &env->vfp.zregs[regno].d[0]; in aa64_vfp_qreg()
3228 /* Shared between translate-sve.c and sve_helper.c. */
3232 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.