Lines Matching +full:1 +full:- +full:4
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
35 #define KVM_HAVE_MCE_INJECTION 1
38 #define EXCP_UDEF 1 /* undefined instruction */
41 #define EXCP_DATA_ABORT 4
67 #define ARMV7M_EXCP_RESET 1
70 #define ARMV7M_EXCP_MEM 4
79 /* ARM-specific interrupt pending bits. */
102 /* ARM-specific extra insn start words:
103 * 1: Conditional execution bits
113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
121 s<2n+1> maps to the most significant half of d<n>
148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
149 * For 64-bit, this is a 2048-bit SVE register.
154 * Qn = regs[n].d[1]:regs[n].d[0]
155 * Dn = regs[n / 2].d[n & 1]
156 * Sn = regs[n / 4].d[n % 4 / 2],
161 * Qn = regs[n].d[1]:regs[n].d[0]
176 # define ARM_MAX_VQ 1
221 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
223 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
224 * DAIF (exception masks) are kept in env->daif
225 * BTYPE is kept in env->btype
226 * SM and ZA are kept in env->svcr
227 * all other bits are stored in their correct places in env->pstate
247 /* These hold r8-r12. */
252 uint32_t CF; /* 0 or 1 */
256 uint32_t QF; /* 0 or 1 */
263 uint64_t elr_el[4]; /* AArch64 exception link regs */
264 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
276 uint64_t csselr_el[4];
285 uint64_t sctlr_el[4];
289 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
292 uint32_t nsacr; /* Non-secure access control register. */
300 uint64_t ttbr0_el[4];
302 union { /* MMU translation table base 1. */
309 uint64_t ttbr1_el[4];
314 uint64_t tcr_el[4];
351 uint64_t esr_el[4];
370 uint64_t far_el[4];
381 uint64_t par_el[4];
410 uint64_t mair_el[4];
419 uint64_t vbar_el[4];
434 uint64_t contextidr_el[4];
443 uint64_t tpidr_el[4];
453 uint64_t tpidrro_el[1];
463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
465 uint32_t c15_threadid; /* TI debugger thread-ID. */
483 * architecturally-correct value is being read/set.
500 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
510 * Fine-Grained Trap registers. We store these as arrays so the
517 uint64_t fgt_exec[1]; /* HFGITR */
529 /* M profile has up to 4 stack pointers:
531 * of the Secure and Non-Secure states. (If the CPU doesn't support
534 * and the non-active SP for the current security state in
574 * code which raises an exception must set cs->exception_index and
576 * will then set the guest-visible registers as part of the exception
601 /* Thumb-2 EE state. */
618 uint32_t qc[4] QEMU_ALIGNED(16);
637 * fp_status_fp16: used for half-precision calculations
639 * standard_fp_status_fp16 : used for half-precision
642 * Half-precision operations are governed by a separate
643 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
646 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
647 * round-to-nearest and is used by any operations (generally
666 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
667 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
673 * Contains the 'val' for the second 64-bit register of LDXP, which comes
674 * from the higher address, not the high part of a complete 128-bit value.
698 uint64_t scxtnum_el[4];
701 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
703 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
787 env->features |= 1ULL << feature; in set_feature()
792 env->features &= ~(1ULL << feature); in unset_feature()
812 PSCI_OFF = 1,
819 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
820 * bytes, i.e. each bit number + 1 is the vector length in quadwords.
873 * pmu_op_finish() - it does not need other handling during migration
920 /* CPU has M-profile DSP extension */
935 * 0 - disabled, 1 - smc, 2 - hvc
941 /* For v8M, initial value of the Non-secure VTOR */
972 /* QOM property to indicate we should use the back-compat CNTFRQ default */
980 /* The instance init functions for implementation-specific subclasses
981 * set these fields to specify the implementation-dependent values of
982 * various constant registers and reset values of non-constant
987 * is used for reset values of non-constant registers; no reset_
993 * you need to also update the 32-bit and 64-bit versions of the
1067 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
1069 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
1081 * big-endian mode). This setting isn't used directly: instead it modifies
1092 /* Used to synchronize KVM and QEMU in-kernel device levels */
1193 * lower exception level. This function does that post-reset CPU setup,
1198 * @target_el must be an EL implemented by the CPU between 1 and 3.
1214 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1215 * The byte at offset i from the start of the in-memory representation contains
1218 * matches QEMU's representation, which is to use an array of host-endian
1220 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1258 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1268 return env->aarch64; in is_a64()
1276 * they are enabled) and the guest-visible values. These two calls must
1308 #define SCTLR_M (1U << 0)
1309 #define SCTLR_A (1U << 1)
1310 #define SCTLR_C (1U << 2)
1311 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1312 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1313 #define SCTLR_SA (1U << 3) /* AArch64 only */
1314 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1315 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1316 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1317 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1318 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1319 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1320 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
1321 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1322 #define SCTLR_ITD (1U << 7) /* v8 onward */
1323 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1324 #define SCTLR_SED (1U << 8) /* v8 onward */
1325 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1326 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1327 #define SCTLR_F (1U << 10) /* up to v6 */
1328 #define SCTLR_SW (1U << 10) /* v7 */
1329 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1330 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1331 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1332 #define SCTLR_I (1U << 12)
1333 #define SCTLR_V (1U << 13) /* AArch32 only */
1334 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1335 #define SCTLR_RR (1U << 14) /* up to v7 */
1336 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1337 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1338 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1339 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1340 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1341 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1342 #define SCTLR_BR (1U << 17) /* PMSA only */
1343 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1344 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1345 #define SCTLR_WXN (1U << 19)
1346 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1347 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1348 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1349 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1350 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1351 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1352 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1353 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1354 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1355 #define SCTLR_VE (1U << 24) /* up to v7 */
1356 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1357 #define SCTLR_EE (1U << 25)
1358 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1359 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1360 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1361 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1362 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1363 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1364 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1365 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1366 #define SCTLR_TE (1U << 30) /* AArch32 only */
1367 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1368 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1369 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1370 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */
1371 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
1372 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1373 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1374 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1375 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1376 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1377 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1378 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1379 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1380 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
1381 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */
1382 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
1383 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
1384 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
1385 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */
1386 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
1387 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
1388 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
1389 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
1390 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
1391 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
1392 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1393 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
1396 #define CPSR_T (1U << 5)
1397 #define CPSR_F (1U << 6)
1398 #define CPSR_I (1U << 7)
1399 #define CPSR_A (1U << 8)
1400 #define CPSR_E (1U << 9)
1403 #define CPSR_IL (1U << 20)
1404 #define CPSR_DIT (1U << 21)
1405 #define CPSR_PAN (1U << 22)
1406 #define CPSR_SSBS (1U << 23)
1407 #define CPSR_J (1U << 24)
1409 #define CPSR_Q (1U << 27)
1410 #define CPSR_V (1U << 28)
1411 #define CPSR_C (1U << 29)
1412 #define CPSR_Z (1U << 30)
1413 #define CPSR_N (1U << 31)
1416 #define ISR_FS (1U << 9)
1417 #define ISR_IS (1U << 10)
1429 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1432 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1433 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1445 * AArch32 mode SPSRs are basically CPSR-format.
1447 #define PSTATE_SP (1U)
1449 #define PSTATE_nRW (1U << 4)
1450 #define PSTATE_F (1U << 6)
1451 #define PSTATE_I (1U << 7)
1452 #define PSTATE_A (1U << 8)
1453 #define PSTATE_D (1U << 9)
1455 #define PSTATE_SSBS (1U << 12)
1456 #define PSTATE_ALLINT (1U << 13)
1457 #define PSTATE_IL (1U << 20)
1458 #define PSTATE_SS (1U << 21)
1459 #define PSTATE_PAN (1U << 22)
1460 #define PSTATE_UAO (1U << 23)
1461 #define PSTATE_DIT (1U << 24)
1462 #define PSTATE_TCO (1U << 25)
1463 #define PSTATE_V (1U << 28)
1464 #define PSTATE_C (1U << 29)
1465 #define PSTATE_Z (1U << 30)
1466 #define PSTATE_N (1U << 31)
1476 #define PSTATE_MODE_EL1t 4
1480 FIELD(SVCR, SM, 0, 1)
1481 FIELD(SVCR, ZA, 1, 1)
1484 FIELD(SMCR, LEN, 0, 4)
1485 FIELD(SMCR, FA64, 31, 1)
1498 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1506 ZF = (env->ZF == 0); in pstate_read()
1507 return (env->NF & 0x80000000) | (ZF << 30) in pstate_read()
1508 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) in pstate_read()
1509 | env->pstate | env->daif | (env->btype << 10); in pstate_read()
1514 env->ZF = (~val) & PSTATE_Z; in pstate_write()
1515 env->NF = val; in pstate_write()
1516 env->CF = (val >> 29) & 1; in pstate_write()
1517 env->VF = (val << 3) & 0x80000000; in pstate_write()
1518 env->daif = val & PSTATE_DAIF; in pstate_write()
1519 env->btype = (val >> 10) & 3; in pstate_write()
1520 env->pstate = val & ~CACHED_PSTATE_BITS; in pstate_write()
1528 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1535 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1547 ZF = (env->ZF == 0); in xpsr_read()
1548 return (env->NF & 0x80000000) | (ZF << 30) in xpsr_read()
1549 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in xpsr_read()
1550 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1551 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1552 | (env->GE << 16) in xpsr_read()
1553 | env->v7m.exception; in xpsr_read()
1556 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1560 env->ZF = (~val) & XPSR_Z; in xpsr_write()
1561 env->NF = val; in xpsr_write()
1562 env->CF = (val >> 29) & 1; in xpsr_write()
1563 env->VF = (val << 3) & 0x80000000; in xpsr_write()
1566 env->QF = ((val & XPSR_Q) != 0); in xpsr_write()
1569 env->GE = (val & XPSR_GE) >> 16; in xpsr_write()
1573 env->thumb = ((val & XPSR_T) != 0); in xpsr_write()
1576 env->condexec_bits &= ~3; in xpsr_write()
1577 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1580 env->condexec_bits &= 3; in xpsr_write()
1581 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1590 #define HCR_VM (1ULL << 0)
1591 #define HCR_SWIO (1ULL << 1)
1592 #define HCR_PTW (1ULL << 2)
1593 #define HCR_FMO (1ULL << 3)
1594 #define HCR_IMO (1ULL << 4)
1595 #define HCR_AMO (1ULL << 5)
1596 #define HCR_VF (1ULL << 6)
1597 #define HCR_VI (1ULL << 7)
1598 #define HCR_VSE (1ULL << 8)
1599 #define HCR_FB (1ULL << 9)
1601 #define HCR_DC (1ULL << 12)
1602 #define HCR_TWI (1ULL << 13)
1603 #define HCR_TWE (1ULL << 14)
1604 #define HCR_TID0 (1ULL << 15)
1605 #define HCR_TID1 (1ULL << 16)
1606 #define HCR_TID2 (1ULL << 17)
1607 #define HCR_TID3 (1ULL << 18)
1608 #define HCR_TSC (1ULL << 19)
1609 #define HCR_TIDCP (1ULL << 20)
1610 #define HCR_TACR (1ULL << 21)
1611 #define HCR_TSW (1ULL << 22)
1612 #define HCR_TPCP (1ULL << 23)
1613 #define HCR_TPU (1ULL << 24)
1614 #define HCR_TTLB (1ULL << 25)
1615 #define HCR_TVM (1ULL << 26)
1616 #define HCR_TGE (1ULL << 27)
1617 #define HCR_TDZ (1ULL << 28)
1618 #define HCR_HCD (1ULL << 29)
1619 #define HCR_TRVM (1ULL << 30)
1620 #define HCR_RW (1ULL << 31)
1621 #define HCR_CD (1ULL << 32)
1622 #define HCR_ID (1ULL << 33)
1623 #define HCR_E2H (1ULL << 34)
1624 #define HCR_TLOR (1ULL << 35)
1625 #define HCR_TERR (1ULL << 36)
1626 #define HCR_TEA (1ULL << 37)
1627 #define HCR_MIOCNCE (1ULL << 38)
1628 #define HCR_TME (1ULL << 39)
1629 #define HCR_APK (1ULL << 40)
1630 #define HCR_API (1ULL << 41)
1631 #define HCR_NV (1ULL << 42)
1632 #define HCR_NV1 (1ULL << 43)
1633 #define HCR_AT (1ULL << 44)
1634 #define HCR_NV2 (1ULL << 45)
1635 #define HCR_FWB (1ULL << 46)
1636 #define HCR_FIEN (1ULL << 47)
1637 #define HCR_GPF (1ULL << 48)
1638 #define HCR_TID4 (1ULL << 49)
1639 #define HCR_TICAB (1ULL << 50)
1640 #define HCR_AMVOFFEN (1ULL << 51)
1641 #define HCR_TOCU (1ULL << 52)
1642 #define HCR_ENSCXT (1ULL << 53)
1643 #define HCR_TTLBIS (1ULL << 54)
1644 #define HCR_TTLBOS (1ULL << 55)
1645 #define HCR_ATA (1ULL << 56)
1646 #define HCR_DCT (1ULL << 57)
1647 #define HCR_TID5 (1ULL << 58)
1648 #define HCR_TWEDEN (1ULL << 59)
1649 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1651 #define SCR_NS (1ULL << 0)
1652 #define SCR_IRQ (1ULL << 1)
1653 #define SCR_FIQ (1ULL << 2)
1654 #define SCR_EA (1ULL << 3)
1655 #define SCR_FW (1ULL << 4)
1656 #define SCR_AW (1ULL << 5)
1657 #define SCR_NET (1ULL << 6)
1658 #define SCR_SMD (1ULL << 7)
1659 #define SCR_HCE (1ULL << 8)
1660 #define SCR_SIF (1ULL << 9)
1661 #define SCR_RW (1ULL << 10)
1662 #define SCR_ST (1ULL << 11)
1663 #define SCR_TWI (1ULL << 12)
1664 #define SCR_TWE (1ULL << 13)
1665 #define SCR_TLOR (1ULL << 14)
1666 #define SCR_TERR (1ULL << 15)
1667 #define SCR_APK (1ULL << 16)
1668 #define SCR_API (1ULL << 17)
1669 #define SCR_EEL2 (1ULL << 18)
1670 #define SCR_EASE (1ULL << 19)
1671 #define SCR_NMEA (1ULL << 20)
1672 #define SCR_FIEN (1ULL << 21)
1673 #define SCR_ENSCXT (1ULL << 25)
1674 #define SCR_ATA (1ULL << 26)
1675 #define SCR_FGTEN (1ULL << 27)
1676 #define SCR_ECVEN (1ULL << 28)
1677 #define SCR_TWEDEN (1ULL << 29)
1678 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1679 #define SCR_TME (1ULL << 34)
1680 #define SCR_AMVOFFEN (1ULL << 35)
1681 #define SCR_ENAS0 (1ULL << 36)
1682 #define SCR_ADEN (1ULL << 37)
1683 #define SCR_HXEN (1ULL << 38)
1684 #define SCR_TRNDR (1ULL << 40)
1685 #define SCR_ENTP2 (1ULL << 41)
1686 #define SCR_GPF (1ULL << 48)
1687 #define SCR_NSE (1ULL << 62)
1708 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1709 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1710 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1711 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1712 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1713 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */
1714 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1715 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1716 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1719 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1720 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1721 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1723 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1731 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */
1732 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */
1733 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */
1734 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */
1735 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */
1736 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */
1737 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */
1738 #define FPSR_V (1 << 28) /* FP overflow flag */
1739 #define FPSR_C (1 << 29) /* FP carry flag */
1740 #define FPSR_Z (1 << 30) /* FP zero flag */
1741 #define FPSR_N (1 << 31) /* FP negative flag */
1802 #define ARM_VFP_FPSCR 1
1809 /* These ones are M-profile only */
1816 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1821 #define ARM_IWMMXT_wCon 1
1830 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1831 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1832 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1833 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1834 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1835 FIELD(V7M_CCR, STKALIGN, 9, 1)
1836 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1837 FIELD(V7M_CCR, DC, 16, 1)
1838 FIELD(V7M_CCR, IC, 17, 1)
1839 FIELD(V7M_CCR, BP, 18, 1)
1840 FIELD(V7M_CCR, LOB, 19, 1)
1841 FIELD(V7M_CCR, TRD, 20, 1)
1844 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1845 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1846 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1847 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1850 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1851 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1852 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1853 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1855 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1856 FIELD(V7M_AIRCR, PRIS, 14, 1)
1857 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1861 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1862 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1863 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1864 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1865 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1866 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1869 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1870 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1871 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1872 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1873 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1874 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1875 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1878 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1879 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1880 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1881 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1882 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1883 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1884 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1892 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1893 FIELD(V7M_HFSR, FORCED, 30, 1)
1894 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1897 FIELD(V7M_DFSR, HALTED, 0, 1)
1898 FIELD(V7M_DFSR, BKPT, 1, 1)
1899 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1900 FIELD(V7M_DFSR, VCATCH, 3, 1)
1901 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1904 FIELD(V7M_SFSR, INVEP, 0, 1)
1905 FIELD(V7M_SFSR, INVIS, 1, 1)
1906 FIELD(V7M_SFSR, INVER, 2, 1)
1907 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1908 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1909 FIELD(V7M_SFSR, LSPERR, 5, 1)
1910 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1911 FIELD(V7M_SFSR, LSERR, 7, 1)
1914 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1915 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1916 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1925 FIELD(V7M_CSSELR, IND, 0, 1)
1926 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1927 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1931 FIELD(V7M_CSSELR, INDEX, 0, 4)
1934 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1935 FIELD(V7M_FPCCR, USER, 1, 1)
1936 FIELD(V7M_FPCCR, S, 2, 1)
1937 FIELD(V7M_FPCCR, THREAD, 3, 1)
1938 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1939 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1940 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1941 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1942 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1943 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1944 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1946 FIELD(V7M_FPCCR, TS, 26, 1)
1947 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1948 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1949 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1950 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1951 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1952 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1964 FIELD(V7M_VPR, MASK01, 16, 4)
1965 FIELD(V7M_VPR, MASK23, 20, 4)
1992 FIELD(CTR_EL0, IMINLINE, 0, 4)
1994 FIELD(CTR_EL0, DMINLINE, 16, 4)
1995 FIELD(CTR_EL0, ERG, 20, 4)
1996 FIELD(CTR_EL0, CWG, 24, 4)
1997 FIELD(CTR_EL0, IDC, 28, 1)
1998 FIELD(CTR_EL0, DIC, 29, 1)
2001 FIELD(MIDR_EL1, REVISION, 0, 4)
2002 FIELD(MIDR_EL1, PARTNUM, 4, 12)
2003 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
2004 FIELD(MIDR_EL1, VARIANT, 20, 4)
2007 FIELD(ID_ISAR0, SWAP, 0, 4)
2008 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
2009 FIELD(ID_ISAR0, BITFIELD, 8, 4)
2010 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
2011 FIELD(ID_ISAR0, COPROC, 16, 4)
2012 FIELD(ID_ISAR0, DEBUG, 20, 4)
2013 FIELD(ID_ISAR0, DIVIDE, 24, 4)
2015 FIELD(ID_ISAR1, ENDIAN, 0, 4)
2016 FIELD(ID_ISAR1, EXCEPT, 4, 4)
2017 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2018 FIELD(ID_ISAR1, EXTEND, 12, 4)
2019 FIELD(ID_ISAR1, IFTHEN, 16, 4)
2020 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2021 FIELD(ID_ISAR1, INTERWORK, 24, 4)
2022 FIELD(ID_ISAR1, JAZELLE, 28, 4)
2024 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2025 FIELD(ID_ISAR2, MEMHINT, 4, 4)
2026 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2027 FIELD(ID_ISAR2, MULT, 12, 4)
2028 FIELD(ID_ISAR2, MULTS, 16, 4)
2029 FIELD(ID_ISAR2, MULTU, 20, 4)
2030 FIELD(ID_ISAR2, PSR_AR, 24, 4)
2031 FIELD(ID_ISAR2, REVERSAL, 28, 4)
2033 FIELD(ID_ISAR3, SATURATE, 0, 4)
2034 FIELD(ID_ISAR3, SIMD, 4, 4)
2035 FIELD(ID_ISAR3, SVC, 8, 4)
2036 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2037 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2038 FIELD(ID_ISAR3, T32COPY, 20, 4)
2039 FIELD(ID_ISAR3, TRUENOP, 24, 4)
2040 FIELD(ID_ISAR3, T32EE, 28, 4)
2042 FIELD(ID_ISAR4, UNPRIV, 0, 4)
2043 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2044 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2045 FIELD(ID_ISAR4, SMC, 12, 4)
2046 FIELD(ID_ISAR4, BARRIER, 16, 4)
2047 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2048 FIELD(ID_ISAR4, PSR_M, 24, 4)
2049 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2051 FIELD(ID_ISAR5, SEVL, 0, 4)
2052 FIELD(ID_ISAR5, AES, 4, 4)
2053 FIELD(ID_ISAR5, SHA1, 8, 4)
2054 FIELD(ID_ISAR5, SHA2, 12, 4)
2055 FIELD(ID_ISAR5, CRC32, 16, 4)
2056 FIELD(ID_ISAR5, RDM, 24, 4)
2057 FIELD(ID_ISAR5, VCMA, 28, 4)
2059 FIELD(ID_ISAR6, JSCVT, 0, 4)
2060 FIELD(ID_ISAR6, DP, 4, 4)
2061 FIELD(ID_ISAR6, FHM, 8, 4)
2062 FIELD(ID_ISAR6, SB, 12, 4)
2063 FIELD(ID_ISAR6, SPECRES, 16, 4)
2064 FIELD(ID_ISAR6, BF16, 20, 4)
2065 FIELD(ID_ISAR6, I8MM, 24, 4)
2067 FIELD(ID_MMFR0, VMSA, 0, 4)
2068 FIELD(ID_MMFR0, PMSA, 4, 4)
2069 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2070 FIELD(ID_MMFR0, SHARELVL, 12, 4)
2071 FIELD(ID_MMFR0, TCM, 16, 4)
2072 FIELD(ID_MMFR0, AUXREG, 20, 4)
2073 FIELD(ID_MMFR0, FCSE, 24, 4)
2074 FIELD(ID_MMFR0, INNERSHR, 28, 4)
2076 FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2077 FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2078 FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2079 FIELD(ID_MMFR1, L1UNISW, 12, 4)
2080 FIELD(ID_MMFR1, L1HVD, 16, 4)
2081 FIELD(ID_MMFR1, L1UNI, 20, 4)
2082 FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2083 FIELD(ID_MMFR1, BPRED, 28, 4)
2085 FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2086 FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2087 FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2088 FIELD(ID_MMFR2, HVDTLB, 12, 4)
2089 FIELD(ID_MMFR2, UNITLB, 16, 4)
2090 FIELD(ID_MMFR2, MEMBARR, 20, 4)
2091 FIELD(ID_MMFR2, WFISTALL, 24, 4)
2092 FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2094 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2095 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2096 FIELD(ID_MMFR3, BPMAINT, 8, 4)
2097 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2098 FIELD(ID_MMFR3, PAN, 16, 4)
2099 FIELD(ID_MMFR3, COHWALK, 20, 4)
2100 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2101 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2103 FIELD(ID_MMFR4, SPECSEI, 0, 4)
2104 FIELD(ID_MMFR4, AC2, 4, 4)
2105 FIELD(ID_MMFR4, XNX, 8, 4)
2106 FIELD(ID_MMFR4, CNP, 12, 4)
2107 FIELD(ID_MMFR4, HPDS, 16, 4)
2108 FIELD(ID_MMFR4, LSM, 20, 4)
2109 FIELD(ID_MMFR4, CCIDX, 24, 4)
2110 FIELD(ID_MMFR4, EVT, 28, 4)
2112 FIELD(ID_MMFR5, ETS, 0, 4)
2113 FIELD(ID_MMFR5, NTLBPA, 4, 4)
2115 FIELD(ID_PFR0, STATE0, 0, 4)
2116 FIELD(ID_PFR0, STATE1, 4, 4)
2117 FIELD(ID_PFR0, STATE2, 8, 4)
2118 FIELD(ID_PFR0, STATE3, 12, 4)
2119 FIELD(ID_PFR0, CSV2, 16, 4)
2120 FIELD(ID_PFR0, AMU, 20, 4)
2121 FIELD(ID_PFR0, DIT, 24, 4)
2122 FIELD(ID_PFR0, RAS, 28, 4)
2124 FIELD(ID_PFR1, PROGMOD, 0, 4)
2125 FIELD(ID_PFR1, SECURITY, 4, 4)
2126 FIELD(ID_PFR1, MPROGMOD, 8, 4)
2127 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2128 FIELD(ID_PFR1, GENTIMER, 16, 4)
2129 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2130 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2131 FIELD(ID_PFR1, GIC, 28, 4)
2133 FIELD(ID_PFR2, CSV3, 0, 4)
2134 FIELD(ID_PFR2, SSBS, 4, 4)
2135 FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2137 FIELD(ID_AA64ISAR0, AES, 4, 4)
2138 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2139 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2140 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2141 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2142 FIELD(ID_AA64ISAR0, TME, 24, 4)
2143 FIELD(ID_AA64ISAR0, RDM, 28, 4)
2144 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2145 FIELD(ID_AA64ISAR0, SM3, 36, 4)
2146 FIELD(ID_AA64ISAR0, SM4, 40, 4)
2147 FIELD(ID_AA64ISAR0, DP, 44, 4)
2148 FIELD(ID_AA64ISAR0, FHM, 48, 4)
2149 FIELD(ID_AA64ISAR0, TS, 52, 4)
2150 FIELD(ID_AA64ISAR0, TLB, 56, 4)
2151 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2153 FIELD(ID_AA64ISAR1, DPB, 0, 4)
2154 FIELD(ID_AA64ISAR1, APA, 4, 4)
2155 FIELD(ID_AA64ISAR1, API, 8, 4)
2156 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2157 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2158 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2159 FIELD(ID_AA64ISAR1, GPA, 24, 4)
2160 FIELD(ID_AA64ISAR1, GPI, 28, 4)
2161 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2162 FIELD(ID_AA64ISAR1, SB, 36, 4)
2163 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2164 FIELD(ID_AA64ISAR1, BF16, 44, 4)
2165 FIELD(ID_AA64ISAR1, DGH, 48, 4)
2166 FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2167 FIELD(ID_AA64ISAR1, XS, 56, 4)
2168 FIELD(ID_AA64ISAR1, LS64, 60, 4)
2170 FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2171 FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2172 FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2173 FIELD(ID_AA64ISAR2, APA3, 12, 4)
2174 FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2175 FIELD(ID_AA64ISAR2, BC, 20, 4)
2176 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2177 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
2178 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
2179 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
2180 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
2181 FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
2182 FIELD(ID_AA64ISAR2, CSSC, 52, 4)
2183 FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
2185 FIELD(ID_AA64PFR0, EL0, 0, 4)
2186 FIELD(ID_AA64PFR0, EL1, 4, 4)
2187 FIELD(ID_AA64PFR0, EL2, 8, 4)
2188 FIELD(ID_AA64PFR0, EL3, 12, 4)
2189 FIELD(ID_AA64PFR0, FP, 16, 4)
2190 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2191 FIELD(ID_AA64PFR0, GIC, 24, 4)
2192 FIELD(ID_AA64PFR0, RAS, 28, 4)
2193 FIELD(ID_AA64PFR0, SVE, 32, 4)
2194 FIELD(ID_AA64PFR0, SEL2, 36, 4)
2195 FIELD(ID_AA64PFR0, MPAM, 40, 4)
2196 FIELD(ID_AA64PFR0, AMU, 44, 4)
2197 FIELD(ID_AA64PFR0, DIT, 48, 4)
2198 FIELD(ID_AA64PFR0, RME, 52, 4)
2199 FIELD(ID_AA64PFR0, CSV2, 56, 4)
2200 FIELD(ID_AA64PFR0, CSV3, 60, 4)
2202 FIELD(ID_AA64PFR1, BT, 0, 4)
2203 FIELD(ID_AA64PFR1, SSBS, 4, 4)
2204 FIELD(ID_AA64PFR1, MTE, 8, 4)
2205 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2206 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2207 FIELD(ID_AA64PFR1, SME, 24, 4)
2208 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2209 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2210 FIELD(ID_AA64PFR1, NMI, 36, 4)
2211 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
2212 FIELD(ID_AA64PFR1, GCS, 44, 4)
2213 FIELD(ID_AA64PFR1, THE, 48, 4)
2214 FIELD(ID_AA64PFR1, MTEX, 52, 4)
2215 FIELD(ID_AA64PFR1, DF2, 56, 4)
2216 FIELD(ID_AA64PFR1, PFAR, 60, 4)
2218 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2219 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2220 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2221 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2222 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2223 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2224 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2225 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2226 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2227 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2228 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2229 FIELD(ID_AA64MMFR0, EXS, 44, 4)
2230 FIELD(ID_AA64MMFR0, FGT, 56, 4)
2231 FIELD(ID_AA64MMFR0, ECV, 60, 4)
2233 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2234 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2235 FIELD(ID_AA64MMFR1, VH, 8, 4)
2236 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2237 FIELD(ID_AA64MMFR1, LO, 16, 4)
2238 FIELD(ID_AA64MMFR1, PAN, 20, 4)
2239 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2240 FIELD(ID_AA64MMFR1, XNX, 28, 4)
2241 FIELD(ID_AA64MMFR1, TWED, 32, 4)
2242 FIELD(ID_AA64MMFR1, ETS, 36, 4)
2243 FIELD(ID_AA64MMFR1, HCX, 40, 4)
2244 FIELD(ID_AA64MMFR1, AFP, 44, 4)
2245 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2246 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2247 FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2248 FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
2250 FIELD(ID_AA64MMFR2, CNP, 0, 4)
2251 FIELD(ID_AA64MMFR2, UAO, 4, 4)
2252 FIELD(ID_AA64MMFR2, LSM, 8, 4)
2253 FIELD(ID_AA64MMFR2, IESB, 12, 4)
2254 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2255 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2256 FIELD(ID_AA64MMFR2, NV, 24, 4)
2257 FIELD(ID_AA64MMFR2, ST, 28, 4)
2258 FIELD(ID_AA64MMFR2, AT, 32, 4)
2259 FIELD(ID_AA64MMFR2, IDS, 36, 4)
2260 FIELD(ID_AA64MMFR2, FWB, 40, 4)
2261 FIELD(ID_AA64MMFR2, TTL, 48, 4)
2262 FIELD(ID_AA64MMFR2, BBM, 52, 4)
2263 FIELD(ID_AA64MMFR2, EVT, 56, 4)
2264 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2266 FIELD(ID_AA64MMFR3, TCRX, 0, 4)
2267 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
2268 FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
2269 FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
2270 FIELD(ID_AA64MMFR3, S1POE, 16, 4)
2271 FIELD(ID_AA64MMFR3, S2POE, 20, 4)
2272 FIELD(ID_AA64MMFR3, AIE, 24, 4)
2273 FIELD(ID_AA64MMFR3, MEC, 28, 4)
2274 FIELD(ID_AA64MMFR3, D128, 32, 4)
2275 FIELD(ID_AA64MMFR3, D128_2, 36, 4)
2276 FIELD(ID_AA64MMFR3, SNERR, 40, 4)
2277 FIELD(ID_AA64MMFR3, ANERR, 44, 4)
2278 FIELD(ID_AA64MMFR3, SDERR, 52, 4)
2279 FIELD(ID_AA64MMFR3, ADERR, 56, 4)
2280 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
2282 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2283 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2284 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2285 FIELD(ID_AA64DFR0, BRPS, 12, 4)
2286 FIELD(ID_AA64DFR0, PMSS, 16, 4)
2287 FIELD(ID_AA64DFR0, WRPS, 20, 4)
2288 FIELD(ID_AA64DFR0, SEBEP, 24, 4)
2289 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2290 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2291 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2292 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2293 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2294 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2295 FIELD(ID_AA64DFR0, BRBE, 52, 4)
2296 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
2297 FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2299 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2300 FIELD(ID_AA64ZFR0, AES, 4, 4)
2301 FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2302 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2303 FIELD(ID_AA64ZFR0, B16B16, 24, 4)
2304 FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2305 FIELD(ID_AA64ZFR0, SM4, 40, 4)
2306 FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2307 FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2308 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2310 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2311 FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
2312 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2313 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2314 FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2315 FIELD(ID_AA64SMFR0, F16F16, 42, 1)
2316 FIELD(ID_AA64SMFR0, B16B16, 43, 1)
2317 FIELD(ID_AA64SMFR0, I16I32, 44, 4)
2318 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2319 FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2320 FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2321 FIELD(ID_AA64SMFR0, FA64, 63, 1)
2323 FIELD(ID_DFR0, COPDBG, 0, 4)
2324 FIELD(ID_DFR0, COPSDBG, 4, 4)
2325 FIELD(ID_DFR0, MMAPDBG, 8, 4)
2326 FIELD(ID_DFR0, COPTRC, 12, 4)
2327 FIELD(ID_DFR0, MMAPTRC, 16, 4)
2328 FIELD(ID_DFR0, MPROFDBG, 20, 4)
2329 FIELD(ID_DFR0, PERFMON, 24, 4)
2330 FIELD(ID_DFR0, TRACEFILT, 28, 4)
2332 FIELD(ID_DFR1, MTPMU, 0, 4)
2333 FIELD(ID_DFR1, HPMN0, 4, 4)
2335 FIELD(DBGDIDR, SE_IMP, 12, 1)
2336 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2337 FIELD(DBGDIDR, VERSION, 16, 4)
2338 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2339 FIELD(DBGDIDR, BRPS, 24, 4)
2340 FIELD(DBGDIDR, WRPS, 28, 4)
2342 FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2343 FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2344 FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2345 FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2346 FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2347 FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2348 FIELD(DBGDEVID, AUXREGS, 24, 4)
2349 FIELD(DBGDEVID, CIDMASK, 28, 4)
2351 FIELD(DBGDEVID1, PCSROFFSET, 0, 4)
2353 FIELD(MVFR0, SIMDREG, 0, 4)
2354 FIELD(MVFR0, FPSP, 4, 4)
2355 FIELD(MVFR0, FPDP, 8, 4)
2356 FIELD(MVFR0, FPTRAP, 12, 4)
2357 FIELD(MVFR0, FPDIVIDE, 16, 4)
2358 FIELD(MVFR0, FPSQRT, 20, 4)
2359 FIELD(MVFR0, FPSHVEC, 24, 4)
2360 FIELD(MVFR0, FPROUND, 28, 4)
2362 FIELD(MVFR1, FPFTZ, 0, 4)
2363 FIELD(MVFR1, FPDNAN, 4, 4)
2364 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2365 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2366 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2367 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2368 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2369 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2370 FIELD(MVFR1, FPHP, 24, 4)
2371 FIELD(MVFR1, SIMDFMAC, 28, 4)
2373 FIELD(MVFR2, SIMDMISC, 0, 4)
2374 FIELD(MVFR2, FPMISC, 4, 4)
2381 FIELD(GPCCR, GPC, 16, 1)
2382 FIELD(GPCCR, GPCP, 17, 1)
2383 FIELD(GPCCR, L0GPTSZ, 20, 4)
2386 FIELD(MFAR, NSE, 62, 1)
2387 FIELD(MFAR, NS, 63, 1)
2389 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2392 * HWCAP bit, remember to update the feature-bit-to-hwcap
2393 * mapping in linux-user/elfload.c:get_elf_hwcap().
2409 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2415 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2417 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2425 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2433 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2436 * if the board doesn't set a value, instead of 1GHz. It is for backwards
2446 return (env->features & (1ULL << feature)) != 0; in arm_feature()
2459 ARMSS_NonSecure = 1,
2464 /* Return true if @space is secure, in the pre-v9 sense. */
2470 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2505 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { in arm_is_el3_or_mon()
2509 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
2545 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled_secstate()
2602 assert(el >= 1 && el <= 3); in arm_el_is_aa64()
2614 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { in arm_el_is_aa64()
2615 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); in arm_el_is_aa64()
2623 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); in arm_el_is_aa64()
2630 * access the secure or non-secure bank of a cp register. When EL3 is
2631 * operating in AArch32 state, the NS-bit determines whether the secure
2634 * accesses are to the non-secure version.
2640 !(env->cp15.scr_el3 & SCR_NS)); in access_secure_reg()
2647 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2652 (_env)->cp15._regname##_s = (_val); \
2654 (_env)->cp15._regname##_ns = (_val); \
2684 return 1; in arm_highest_el()
2690 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2700 !(env->v7m.control[env->v7m.secure] & 1); in arm_current_el()
2704 return extract32(env->pstate, 2, 2); in arm_current_el()
2707 switch (env->uncached_cpsr & 0x1f) { in arm_current_el()
2716 /* If EL3 is 32-bit then all secure privileged modes run in in arm_current_el()
2722 return 1; in arm_current_el()
2737 * Note that we do not stop early on failure -- we will attempt
2754 * values in the list if the previous list->cpustate sync actually
2760 * Note that we do not stop early on failure -- we will attempt
2770 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2774 * If EL3 is 64-bit:
2775 * + NonSecure EL1 & 0 stage 1
2778 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2779 * + Secure EL1 & 0 stage 1
2783 * + Realm EL1 & 0 stage 1 (FEAT_RME)
2787 * If EL3 is 32-bit:
2788 * + NonSecure PL1 & 0 stage 1
2795 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2796 * because they may differ in access permissions even if the VA->PA map is
2798 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2803 * handling via the TLB. The only way to do a stage 1 translation without
2805 * which can be slow-pathed and always do a page table walk.
2807 * lookup or when loading the descriptors during a stage 1 page table walk,
2809 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2817 * 7. we fold together most secure and non-secure regimes for A-profile,
2819 * process of switching between secure and non-secure is
2826 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
2827 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
2828 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
2844 * EL2 for cores like the Cortex-R52).
2859 * are not quite the same -- different CPU types (most notably M profile
2894 * A-profile.
2897 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2900 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2916 /* TLBs with 1-1 mapping to the physical address spaces. */
2927 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2931 * M-profile.
2944 * Bit macros for the core-mmu-index values for each index,
2948 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2981 ARMASIdx_S = 1,
3000 return idx - ARMMMUIdx_Phys_S; in arm_phys_to_space()
3008 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; in arm_v7m_csselr_razwi()
3014 /* We need not implement SCTLR.ITD in user-mode emulation, so in arm_sctlr_b()
3015 * let linux-user ignore the fact that it conflicts with SCTLR_B. in arm_sctlr_b()
3016 * This lets people run BE32 binaries with "-cpu any". in arm_sctlr_b()
3021 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
3032 * architecture (as word-invariant big-endianness), where loads in arm_cpu_data_is_big_endian_a32()
3037 * In user mode, however, we model BE32 as byte-invariant in arm_cpu_data_is_big_endian_a32()
3038 * big-endianness (because user-only code cannot tell the in arm_cpu_data_is_big_endian_a32()
3047 return env->uncached_cpsr & CPSR_E; in arm_cpu_data_is_big_endian_a32()
3055 /* Return true if the processor is in big-endian mode. */
3067 #include "exec/cpu-all.h"
3070 * We have more than 32-bits worth of state per TB, so we split the data
3071 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3078 * address size, flags2 always has 64-bits for A64, and a minimum of
3079 * 32-bits for A32 and M32.
3081 * The bits for 32-bit A-profile and M-profile partially overlap:
3084 * +-------------+----------+----------------+
3086 * | TBFLAG_AM32 | +-----+----------+
3088 * +-------------+----------------+----------+
3091 * Unless otherwise noted, these bits are cached in env->hflags.
3093 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3094 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3095 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
3096 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3097 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3098 /* Target EL if we take a floating-point-disabled exception */
3101 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
3102 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
3103 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
3104 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
3107 * Bit usage when in AArch32 state, both A- and M-profile.
3110 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
3113 * Bit usage when in AArch32 state, for A-profile only.
3124 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
3125 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
3126 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3132 FIELD(TBFLAG_A32, NS, 10, 1)
3137 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3140 * Bit usage when in AArch32 state, for M-profile only.
3143 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3144 /* Whether we should generate stack-limit checks */
3145 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3147 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
3149 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
3151 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
3153 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
3155 FIELD(TBFLAG_M32, SECURE, 6, 1)
3163 FIELD(TBFLAG_A64, VL, 4, 4)
3164 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3165 FIELD(TBFLAG_A64, BT, 9, 1)
3168 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3169 FIELD(TBFLAG_A64, ATA, 15, 1)
3171 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3172 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3174 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3175 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3176 FIELD(TBFLAG_A64, SVL, 24, 4)
3178 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3179 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1)
3180 FIELD(TBFLAG_A64, NAA, 30, 1)
3181 FIELD(TBFLAG_A64, ATA0, 31, 1)
3182 FIELD(TBFLAG_A64, NV, 32, 1)
3183 FIELD(TBFLAG_A64, NV1, 33, 1)
3184 FIELD(TBFLAG_A64, NV2, 34, 1)
3186 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1)
3187 /* Set if FEAT_NV2 RAM accesses are big-endian */
3188 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
3216 * Return the VL cached within env->hflags, in units of quadwords.
3220 return EX_TBFLAG_A64(env->hflags, VL) + 1; in sve_vq()
3227 * Return the SVL cached within env->hflags, in units of quadwords.
3231 return EX_TBFLAG_A64(env->hflags, SVL) + 1; in sme_vq()
3237 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. in bswap_code()
3238 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 in bswap_code()
3239 * would also end up as a mixed-endian mode with BE code, LE data. in bswap_code()
3262 QEMU_PSCI_CONDUIT_SMC = 1,
3290 * Note that if a pre-change hook is called, any registered post-change hooks
3303 * if pre-change hooks have been.
3316 * Return a pointer to the Dn register within env in 32-bit mode.
3320 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg()
3325 * Return a pointer to the Qn register within env in 32-bit mode.
3329 return &env->vfp.zregs[regno].d[0]; in aa32_vfp_qreg()
3334 * Return a pointer to the Qn register within env in 64-bit mode.
3338 return &env->vfp.zregs[regno].d[0]; in aa64_vfp_qreg()
3341 /* Shared between translate-sve.c and sve_helper.c. */
3345 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3354 #define LOG2_TAG_GRANULE 4
3355 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
3358 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1))
3371 * include/exec/cpu_ldst.h, and not some place linux-user specific.
3376 if (env->tagged_addr_enable) { in cpu_untagged_addr()