target/arm/cpu-features.h

2  * QEMU Arm CPU -- feature test functions
24 #include "qemu/host-utils.h"
26 #include "cpu-sysregs.h"
30  * Functions which test 32-bit ID registers should have _aa32_ in
31  * their name. Functions which test 64-bit ID registers should have
37  * we let this system register bit be set" tests where the 32-bit
45  * 32-bit feature tests via id registers.
59     /* (M-profile) low-overhead loops and branch future */  in isar_feature_aa32_lob()
151      * Return true if M-profile state handling insns  in isar_feature_aa32_m_sec_state()
159     /* Sadly this is encoded differently for A-profile and M-profile */  in isar_feature_aa32_fp16_arith()
161         return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;  in isar_feature_aa32_fp16_arith()
163         return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;  in isar_feature_aa32_fp16_arith()
171      * We must check for M-profile as the MVFR1 field means something  in isar_feature_aa32_mve()
172      * else for A-profile.  in isar_feature_aa32_mve()
175         FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;  in isar_feature_aa32_mve()
182      * We must check for M-profile as the MVFR1 field means something  in isar_feature_aa32_mve_fp()
183      * else for A-profile.  in isar_feature_aa32_mve_fp()
186         FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;  in isar_feature_aa32_mve_fp()
193      * In this case, a minimum of VFP w/ D0-D15.  in isar_feature_aa32_vfp_simd()
195     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;  in isar_feature_aa32_vfp_simd()
200     /* Return true if D16-D31 are implemented */  in isar_feature_aa32_simd_r32()
201     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;  in isar_feature_aa32_simd_r32()
206     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;  in isar_feature_aa32_fpshvec()
212     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;  in isar_feature_aa32_fpsp_v2()
218     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;  in isar_feature_aa32_fpsp_v3()
224     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;  in isar_feature_aa32_fpdp_v2()
230     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;  in isar_feature_aa32_fpdp_v3()
245     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;  in isar_feature_aa32_fp16_spconv()
250     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;  in isar_feature_aa32_fp16_dpconv()
258  * a VFP-no-Neon core or vice-versa.
262     return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;  in isar_feature_aa32_simdfmac()
267     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;  in isar_feature_aa32_vsel()
272     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;  in isar_feature_aa32_vcvt_dr()
277     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;  in isar_feature_aa32_vrint()
282     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;  in isar_feature_aa32_vminmaxnm()
302     /* 0xf means "non-standard IMPDEF PMU" */  in isar_feature_aa32_pmuv3p1()
309     /* 0xf means "non-standard IMPDEF PMU" */  in isar_feature_aa32_pmuv3p4()
316     /* 0xf means "non-standard IMPDEF PMU" */  in isar_feature_aa32_pmuv3p5()
373     return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;  in isar_feature_aa32_doublelock()
377  * 64-bit feature tests via id registers.
502      * Architecturally, only one of {APA,API,APA3} may be active (non-zero)  in isar_feature_pauth_feature()
514      * predicate controls migration of the 128-bit keys.  in isar_feature_aa64_pauth()
1059  * Feature tests for "does this exist in either 32-bit or 64-bit?"
1139          * The 32-bit CCSIDR format is:  in make_ccsidr()
1140          *   [27:13] number of sets - 1  in make_ccsidr()
1141          *   [12:3]  associativity - 1  in make_ccsidr()
1142          *   [2:0]   log2(linesize) - 4  in make_ccsidr()
1146         ccsidr = deposit32(ccsidr, 13, 15, sets - 1);  in make_ccsidr()
1147         ccsidr = deposit32(ccsidr,  3, 10, assoc - 1);  in make_ccsidr()
1148         ccsidr = deposit32(ccsidr,  0,  3, lg_linesize - 4);  in make_ccsidr()
1151          * The 64-bit CCSIDR_EL1 format is:  in make_ccsidr()
1152          *   [55:32] number of sets - 1  in make_ccsidr()
1153          *   [23:3]  associativity - 1  in make_ccsidr()
1154          *   [2:0]   log2(linesize) - 4  in make_ccsidr()
1157         ccsidr = deposit64(ccsidr, 32, 24, sets - 1);  in make_ccsidr()
1158         ccsidr = deposit64(ccsidr,  3, 21, assoc - 1);  in make_ccsidr()
1159         ccsidr = deposit64(ccsidr,  0,  3, lg_linesize - 4);  in make_ccsidr()
1169     ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })