Lines Matching +full:- +full:- +full:disable +full:- +full:sparse
3 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cpu-features.h"
31 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in access_tpm()
71 return -1; in swinc_ns_per()
134 return -1; in zero_event_ns_per()
175 * should first be updated to something sparse instead of the current
193 * Empty supported_event_map and cpu->pmceid[01] before adding supported in pmu_init()
199 cpu->pmceid0 = 0; in pmu_init()
200 cpu->pmceid1 = 0; in pmu_init()
204 assert(cnt->number <= MAX_EVENT_ID); in pmu_init()
206 assert(cnt->number <= 0x3f); in pmu_init()
208 if (cnt->supported(&cpu->env)) { in pmu_init()
209 supported_event_map[cnt->number] = i; in pmu_init()
210 uint64_t event_mask = 1ULL << (cnt->number & 0x1f); in pmu_init()
211 if (cnt->number & 0x20) { in pmu_init()
212 cpu->pmceid1 |= event_mask; in pmu_init()
214 cpu->pmceid0 |= event_mask; in pmu_init()
240 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { in do_pmreg_access()
253 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in do_pmreg_access()
280 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 in pmreg_access_xevcntr()
295 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 in pmreg_access_swinc()
310 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { in pmreg_access_selr()
324 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 in pmreg_access_ccntr()
347 * We might be called for M-profile cores where MDCR_EL2 doesn't in pmu_counter_enabled()
348 * exist and arm_mdcr_el2_eff() will assert, so this early-exit check in pmu_counter_enabled()
360 e = env->cp15.c9_pmcr & PMCRE; in pmu_counter_enabled()
364 enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
371 prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
376 * The cycle counter defaults to running. PMCR.DP says "disable in pmu_counter_enabled()
378 * Some MDCR bits disable the cycle counter specifically. in pmu_counter_enabled()
380 prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; in pmu_counter_enabled()
383 prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); in pmu_counter_enabled()
392 filter = env->cp15.pmccfiltr_el0; in pmu_counter_enabled()
394 filter = env->cp15.c14_pmevtyper[counter]; in pmu_counter_enabled()
432 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_update_irq()
433 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq()
442 * (64-bit) cycle counter PMCR.D has no effect. in pmccntr_clockdiv_enabled()
444 return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; in pmccntr_clockdiv_enabled()
463 bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; in pmevcntr_is_64_bit()
464 int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; in pmevcntr_is_64_bit()
470 return env->cp15.c9_pmcr & PMCRLP; in pmevcntr_is_64_bit()
474 * Ensure c15_ccnt is the guest-visible count so that operations such as
476 * etc. can be done logically. This is essentially a no-op if the counter is
489 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; in pmccntr_op_start()
491 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ in pmccntr_op_start()
493 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { in pmccntr_op_start()
494 env->cp15.c9_pmovsr |= (1ULL << 31); in pmccntr_op_start()
498 env->cp15.c15_ccnt = new_pmccntr; in pmccntr_op_start()
500 env->cp15.c15_ccnt_delta = cycles; in pmccntr_op_start()
505 * guest-visible count. A call to pmccntr_op_finish should follow every call to
513 uint64_t remaining_cycles = -env->cp15.c15_ccnt; in pmccntr_op_finish()
514 if (!(env->cp15.c9_pmcr & PMCRLC)) { in pmccntr_op_finish()
525 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); in pmccntr_op_finish()
530 uint64_t prev_cycles = env->cp15.c15_ccnt_delta; in pmccntr_op_finish()
534 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; in pmccntr_op_finish()
541 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_start()
549 uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; in pmevcntr_op_start()
553 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { in pmevcntr_op_start()
554 env->cp15.c9_pmovsr |= (1 << counter); in pmevcntr_op_start()
557 env->cp15.c14_pmevcntr[counter] = new_pmevcntr; in pmevcntr_op_start()
559 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevcntr_op_start()
566 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_finish()
568 uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); in pmevcntr_op_finish()
582 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); in pmevcntr_op_finish()
587 env->cp15.c14_pmevcntr_delta[counter] -= in pmevcntr_op_finish()
588 env->cp15.c14_pmevcntr[counter]; in pmevcntr_op_finish()
612 pmu_op_start(&cpu->env); in pmu_pre_el_change()
617 pmu_op_finish(&cpu->env); in pmu_post_el_change()
627 * has the effect of setting the cpu->pmu_timer to the next earliest time a in arm_pmu_timer_cb()
630 pmu_op_start(&cpu->env); in arm_pmu_timer_cb()
631 pmu_op_finish(&cpu->env); in arm_pmu_timer_cb()
641 env->cp15.c15_ccnt = 0; in pmcr_write()
647 env->cp15.c14_pmevcntr[i] = 0; in pmcr_write()
651 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in pmcr_write()
652 env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); in pmcr_write()
659 uint64_t pmcr = env->cp15.c9_pmcr; in pmcr_read()
667 pmcr |= (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; in pmcr_read()
685 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { in pmswinc_write()
692 new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; in pmswinc_write()
697 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { in pmswinc_write()
698 env->cp15.c9_pmovsr |= (1 << i); in pmswinc_write()
702 env->cp15.c14_pmevcntr[i] = new_pmswinc; in pmswinc_write()
713 ret = env->cp15.c15_ccnt; in pmccntr_read()
727 env->cp15.c9_pmselr = value & 0x1f; in pmselr_write()
734 env->cp15.c15_ccnt = value; in pmccntr_write()
750 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; in pmccfiltr_write()
759 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | in pmccfiltr_write_a32()
767 return env->cp15.pmccfiltr_el0 & PMCCFILTR; in pmccfiltr_read_a32()
775 env->cp15.c9_pmcnten |= value; in pmcntenset_write()
784 env->cp15.c9_pmcnten &= ~value; in pmcntenclr_write()
792 env->cp15.c9_pmovsr &= ~value; in pmovsr_write()
800 env->cp15.c9_pmovsr |= value; in pmovsset_write()
818 uint16_t old_event = env->cp15.c14_pmevtyper[counter] & in pmevtyper_write()
827 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevtyper_write()
830 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; in pmevtyper_write()
844 return env->cp15.pmccfiltr_el0; in pmevtyper_read()
846 return env->cp15.c14_pmevtyper[counter]; in pmevtyper_read()
859 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_writefn()
866 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_rawwrite()
867 env->cp15.c14_pmevtyper[counter] = value; in pmevtyper_rawwrite()
881 env->cp15.c14_pmevcntr_delta[counter] = in pmevtyper_rawwrite()
888 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_readfn()
895 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevtyper_write()
900 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevtyper_read()
912 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_write()
927 ret = env->cp15.c14_pmevcntr[counter]; in pmevcntr_read()
946 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_writefn()
952 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_readfn()
959 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawwrite()
961 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_rawwrite()
967 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawread()
969 return env->cp15.c14_pmevcntr[counter]; in pmevcntr_rawread()
975 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevcntr_write()
980 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevcntr_read()
987 env->cp15.c9_pmuserenr = value & 0xf; in pmuserenr_write()
989 env->cp15.c9_pmuserenr = value & 1; in pmuserenr_write()
998 env->cp15.c9_pminten |= value; in pmintenset_write()
1006 env->cp15.c9_pminten &= ~value; in pmintenclr_write()
1194 CPUARMState *env = &cpu->env; in define_pm_cpregs()
1219 .resetvalue = cpu->isar.reset_pmcr_el0, in define_pm_cpregs()
1228 * 32-bit AArch32 PMCCNTR. We don't expose this to GDB if the in define_pm_cpregs()
1229 * new-in-v8 PMUv3 64-bit AArch32 PMCCNTR register is implemented in define_pm_cpregs()
1293 .resetvalue = extract64(cpu->pmceid0, 0, 32) }, in define_pm_cpregs()
1298 .resetvalue = cpu->pmceid0 }, in define_pm_cpregs()
1303 .resetvalue = extract64(cpu->pmceid1, 0, 32) }, in define_pm_cpregs()
1308 .resetvalue = cpu->pmceid1 }, in define_pm_cpregs()
1309 /* AArch32 64-bit PMCCNTR view: added in PMUv3 with Armv8 */ in define_pm_cpregs()
1326 .resetvalue = extract64(cpu->pmceid0, 32, 32) }, in define_pm_cpregs()
1331 .resetvalue = extract64(cpu->pmceid1, 32, 32) }, in define_pm_cpregs()