Lines Matching full:ra

118         "t10", "t11", "ra", "t12", "at", "gp", "sp"  in alpha_translate_init()
314 static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, in gen_load_fp() argument
318 if (likely(ra != 31)) { in gen_load_fp()
321 func(ctx, cpu_fir[ra], addr); in gen_load_fp()
325 static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, in gen_load_int() argument
330 /* LDQ_U with ra $31 is UNOP. Other various loads are forms of in gen_load_int()
333 if (unlikely(ra == 31)) { in gen_load_int()
345 dest = ctx->ir[ra]; in gen_load_int()
380 static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, in gen_store_fp() argument
385 func(ctx, load_fpr(ctx, ra), addr); in gen_store_fp()
388 static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, in gen_store_int() argument
401 src = load_gpr(ctx, ra); in gen_store_int()
405 static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb, in gen_store_conditional() argument
422 load_gpr(ctx, ra), mem_idx, op); in gen_store_conditional()
425 if (ra != 31) { in gen_store_conditional()
426 tcg_gen_setcond_i64(TCG_COND_EQ, ctx->ir[ra], val, cpu_lock_value); in gen_store_conditional()
431 if (ra != 31) { in gen_store_conditional()
432 tcg_gen_movi_i64(ctx->ir[ra], 0); in gen_store_conditional()
458 static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) in gen_bdirect() argument
460 if (ra != 31) { in gen_bdirect()
461 gen_pc_disp(ctx, ctx->ir[ra], 0); in gen_bdirect()
464 /* Notice branch-to-next; used to initialize RA with the PC. */ in gen_bdirect()
485 static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra, in gen_bcond() argument
488 return gen_bcond_internal(ctx, cond, load_gpr(ctx, ra), in gen_bcond()
526 static DisasJumpType gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, in gen_fbcond() argument
530 TCGv_i64 tmp = gen_fold_mzero(&cond, &imm, load_fpr(ctx, ra)); in gen_fbcond()
534 static void gen_fcmov(DisasContext *ctx, TCGCond cond, int ra, int rb, int rc) in gen_fcmov() argument
537 TCGv_i64 tmp = gen_fold_mzero(&cond, &imm, load_fpr(ctx, ra)); in gen_fcmov()
781 int ra, int rb, int rc, int fn11) in gen_ieee_arith3() argument
788 va = gen_ieee_input(ctx, ra, fn11, 0); in gen_ieee_arith3()
798 int ra, int rb, int rc, int fn11) \
800 gen_ieee_arith3(ctx, gen_helper_##name, ra, rb, rc, fn11); \
813 int ra, int rb, int rc, int fn11) in IEEE_ARITH3()
817 va = gen_ieee_input(ctx, ra, fn11, 1); in IEEE_ARITH3()
827 int ra, int rb, int rc, int fn11) \
829 gen_ieee_compare(ctx, gen_helper_##name, ra, rb, rc, fn11); \
1030 static void gen_rx(DisasContext *ctx, int ra, int set) in gen_rx() argument
1032 if (ra != 31) { in gen_rx()
1033 ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); in gen_rx()
1370 uint8_t opc, ra, rb, rc, fpfn, fn7, lit; in translate_one() local
1378 ra = extract32(insn, 21, 5); in translate_one()
1431 va = dest_gpr(ctx, ra); in translate_one()
1443 gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0); in translate_one()
1447 gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 1, 0); in translate_one()
1452 gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0); in translate_one()
1457 gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0); in translate_one()
1462 gen_store_int(ctx, ra, rb, disp16, MO_UB, 0); in translate_one()
1466 gen_store_int(ctx, ra, rb, disp16, MO_LEUQ, 1); in translate_one()
1473 if (ra == 31) { in translate_one()
1486 va = load_gpr(ctx, ra); in translate_one()
1514 if (ra == 31) { in translate_one()
1642 if (ra == 31) { in translate_one()
1657 if (fn7 == 0x28 && ra == 31) { in translate_one()
1663 va = load_gpr(ctx, ra); in translate_one()
1721 REQUIRE_REG_31(ra); in translate_one()
1736 REQUIRE_REG_31(ra); in translate_one()
1746 va = load_gpr(ctx, ra); in translate_one()
1889 va = load_gpr(ctx, ra); in translate_one()
1936 va = load_gpr(ctx, ra); in translate_one()
1942 REQUIRE_REG_31(ra); in translate_one()
1949 REQUIRE_REG_31(ra); in translate_one()
1958 va = load_gpr(ctx, ra); in translate_one()
1966 va = load_gpr(ctx, ra); in translate_one()
1971 REQUIRE_REG_31(ra); in translate_one()
1978 REQUIRE_REG_31(ra); in translate_one()
1992 va = load_fpr(ctx, ra); in translate_one()
2016 REQUIRE_REG_31(ra); in translate_one()
2055 REQUIRE_REG_31(ra); in translate_one()
2061 REQUIRE_REG_31(ra); in translate_one()
2065 REQUIRE_REG_31(ra); in translate_one()
2071 REQUIRE_REG_31(ra); in translate_one()
2077 REQUIRE_REG_31(ra); in translate_one()
2092 gen_adds(ctx, ra, rb, rc, fn11); in translate_one()
2097 gen_subs(ctx, ra, rb, rc, fn11); in translate_one()
2102 gen_muls(ctx, ra, rb, rc, fn11); in translate_one()
2107 gen_divs(ctx, ra, rb, rc, fn11); in translate_one()
2112 gen_addt(ctx, ra, rb, rc, fn11); in translate_one()
2117 gen_subt(ctx, ra, rb, rc, fn11); in translate_one()
2122 gen_mult(ctx, ra, rb, rc, fn11); in translate_one()
2127 gen_divt(ctx, ra, rb, rc, fn11); in translate_one()
2132 gen_cmptun(ctx, ra, rb, rc, fn11); in translate_one()
2137 gen_cmpteq(ctx, ra, rb, rc, fn11); in translate_one()
2142 gen_cmptlt(ctx, ra, rb, rc, fn11); in translate_one()
2147 gen_cmptle(ctx, ra, rb, rc, fn11); in translate_one()
2150 REQUIRE_REG_31(ra); in translate_one()
2162 REQUIRE_REG_31(ra); in translate_one()
2168 REQUIRE_REG_31(ra); in translate_one()
2174 REQUIRE_REG_31(ra); in translate_one()
2187 REQUIRE_REG_31(ra); in translate_one()
2200 va = load_fpr(ctx, ra); in translate_one()
2201 if (ra == rb) { in translate_one()
2215 va = load_fpr(ctx, ra); in translate_one()
2223 va = load_fpr(ctx, ra); in translate_one()
2229 va = load_fpr(ctx, ra); in translate_one()
2240 va = dest_fpr(ctx, ra); in translate_one()
2246 gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc); in translate_one()
2251 gen_fcmov(ctx, TCG_COND_NE, ra, rb, rc); in translate_one()
2256 gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc); in translate_one()
2261 gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc); in translate_one()
2266 gen_fcmov(ctx, TCG_COND_LE, ra, rb, rc); in translate_one()
2271 gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc); in translate_one()
2276 REQUIRE_REG_31(ra); in translate_one()
2316 va = dest_gpr(ctx, ra); in translate_one()
2324 gen_rx(ctx, ra, 0); in translate_one()
2331 gen_rx(ctx, ra, 1); in translate_one()
2350 va = dest_gpr(ctx, ra); in translate_one()
2361 if (ra != 31) { in translate_one()
2364 gen_pc_disp(ctx, ctx->ir[ra], 0); in translate_one()
2379 va = dest_gpr(ctx, ra); in translate_one()
2463 va = load_fpr(ctx, ra); in translate_one()
2471 va = load_fpr(ctx, ra); in translate_one()
2482 REQUIRE_REG_31(ra); in translate_one()
2488 REQUIRE_REG_31(ra); in translate_one()
2494 REQUIRE_REG_31(ra); in translate_one()
2502 va = load_gpr(ctx, ra); in translate_one()
2508 REQUIRE_REG_31(ra); in translate_one()
2515 REQUIRE_REG_31(ra); in translate_one()
2522 REQUIRE_REG_31(ra); in translate_one()
2529 REQUIRE_REG_31(ra); in translate_one()
2536 REQUIRE_REG_31(ra); in translate_one()
2543 REQUIRE_REG_31(ra); in translate_one()
2550 va = load_gpr(ctx, ra); in translate_one()
2556 va = load_gpr(ctx, ra); in translate_one()
2562 va = load_gpr(ctx, ra); in translate_one()
2568 va = load_gpr(ctx, ra); in translate_one()
2574 va = load_gpr(ctx, ra); in translate_one()
2580 va = load_gpr(ctx, ra); in translate_one()
2586 va = load_gpr(ctx, ra); in translate_one()
2592 va = load_gpr(ctx, ra); in translate_one()
2645 va = load_gpr(ctx, ra); in translate_one()
2653 va = load_gpr(ctx, ra); in translate_one()
2661 ret = gen_store_conditional(ctx, ra, rb, disp12, in translate_one()
2666 ret = gen_store_conditional(ctx, ra, rb, disp12, in translate_one()
2714 gen_load_fp(ctx, ra, rb, disp16, gen_ldf); in translate_one()
2719 gen_load_fp(ctx, ra, rb, disp16, gen_ldg); in translate_one()
2724 gen_load_fp(ctx, ra, rb, disp16, gen_lds); in translate_one()
2729 gen_load_fp(ctx, ra, rb, disp16, gen_ldt); in translate_one()
2734 gen_store_fp(ctx, ra, rb, disp16, gen_stf); in translate_one()
2739 gen_store_fp(ctx, ra, rb, disp16, gen_stg); in translate_one()
2744 gen_store_fp(ctx, ra, rb, disp16, gen_sts); in translate_one()
2749 gen_store_fp(ctx, ra, rb, disp16, gen_stt); in translate_one()
2753 gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0); in translate_one()
2757 gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 0, 0); in translate_one()
2761 gen_load_int(ctx, ra, rb, disp16, MO_LESL | MO_ALIGN, 0, 1); in translate_one()
2765 gen_load_int(ctx, ra, rb, disp16, MO_LEUQ | MO_ALIGN, 0, 1); in translate_one()
2769 gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0); in translate_one()
2773 gen_store_int(ctx, ra, rb, disp16, MO_LEUQ, 0); in translate_one()
2777 ret = gen_store_conditional(ctx, ra, rb, disp16, in translate_one()
2782 ret = gen_store_conditional(ctx, ra, rb, disp16, in translate_one()
2787 ret = gen_bdirect(ctx, ra, disp21); in translate_one()
2791 ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21); in translate_one()
2795 ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21); in translate_one()
2799 ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21); in translate_one()
2803 ret = gen_bdirect(ctx, ra, disp21); in translate_one()
2807 ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21); in translate_one()
2811 ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21); in translate_one()
2815 ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21); in translate_one()
2819 ret = gen_bcond(ctx, TCG_COND_TSTEQ, ra, disp21); in translate_one()
2823 ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21); in translate_one()
2827 ret = gen_bcond(ctx, TCG_COND_LT, ra, disp21); in translate_one()
2831 ret = gen_bcond(ctx, TCG_COND_LE, ra, disp21); in translate_one()
2835 ret = gen_bcond(ctx, TCG_COND_TSTNE, ra, disp21); in translate_one()
2839 ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21); in translate_one()
2843 ret = gen_bcond(ctx, TCG_COND_GE, ra, disp21); in translate_one()
2847 ret = gen_bcond(ctx, TCG_COND_GT, ra, disp21); in translate_one()