Lines Matching defs:barrier

20 /* Compiler barrier */
21 #define barrier()   ({ asm volatile("" ::: "memory"); (void)0; })
29  *__atomic_thread_fence does not include a compiler barrier; instead,
30  * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
31  * semantics. If smp_wmb() is a no-op, absence of the barrier means that
32  * the compiler is free to reorder stores on each side of the barrier.
36 #define smp_mb()                     ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
37 #define smp_mb_release()             ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
38 #define smp_mb_acquire()             ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
41  * no processors except Alpha need a barrier here.  Leave it in if
45 #define smp_read_barrier_depends()   ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); })
49 #define smp_read_barrier_depends()   barrier()
53  * A signal barrier forces all pending local memory ops to be observed before
55  * the same as barrier(), but since we have the correct builtin, use it.
69  * no explicit memory barrier for the processor.