Lines Matching defs:self

272     fn clear_valset(&mut self) {  in clear_valset()
284 fn calculate_cmp64(&self, cur_tick: u64, target: u64) -> u64 { in calculate_cmp64()
325 fn set_irq(&mut self, set: bool) { in set_irq()
351 fn update_irq(&mut self, set: bool) { in update_irq()
360 fn arm_timer(&mut self, tick: u64) { in arm_timer()
372 fn set_timer(&mut self) { in set_timer()
389 fn del_timer(&mut self) { in del_timer()
402 fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) { in set_tn_cfg_reg()
432 fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, val: u64) { in set_tn_cmp_reg()
462 fn set_tn_fsb_route_reg(&mut self, shift: u32, len: u32, val: u64) { in set_tn_fsb_route_reg()
466 fn reset(&mut self) { in reset()
481 fn callback(&mut self) { in callback()
502 const fn read(&self, reg: TimerRegister) -> u64 { in read()
511 fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u32) { in write()
583 fn is_timer_int_active(&self, index: usize) -> bool { in is_timer_int_active()
591 fn get_ns(&self, tick: u64) -> u64 { in get_ns()
595 fn handle_legacy_irq(&self, irq: u32, level: u32) { in handle_legacy_irq()
623 fn update_int_status(&self, index: u32, level: bool) { in update_int_status()
629 fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) { in set_cfg_reg()
672 fn set_int_status_reg(&self, shift: u32, _len: u32, val: u64) { in set_int_status_reg()
684 fn set_counter_reg(&self, shift: u32, len: u32, val: u64) { in set_counter_reg()
720 fn post_init(&self) { in post_init()
754 fn reset_hold(&self, _type: ResetType) { in reset_hold()
774 fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode<'_> { in decode()
799 fn read(&self, addr: hwaddr, size: u32) -> u64 { in read()
826 fn write(&self, addr: hwaddr, value: u64, size: u32) { in write()
858 fn post_load(&self, _version_id: u8) -> i32 { in post_load()
883 fn validate_num_timers(&self, _version_id: u8) -> bool { in validate_num_timers()