3 // SPDX-License-Identifier: GPL-2.0-or-later
6 //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
12 use bits::bits;
21     /// Data Register
23     /// A write to this register initiates the actual data transmission
40     /// `IrDA` Low-Power Counter Register
48     /// line control register (data frame format)
76 /// Receive Status Register / Data Register common error bits
91 /// Data Register, `UARTDR`
93 /// The `UARTDR` register is the data register; write for TX and
94 /// read for RX. It is a 12-bit register, where bits 7..0 are the
95 /// character and bits 11..8 are error bits.
99 pub struct Data {  struct
100     pub data: u8,  field
104 impl_vmstate_bitsized!(Data);  argument
106 impl Data {  impl
107     // bilge is not very const-friendly, unfortunately
114 /// status error bits that can be found in bits 11..8 of the UARTDR
116 /// status bits correspond to that character that was just read.
121 /// bits.
131     pub fn set_from_data(&mut self, data: Data) {  in set_from_data()  argument
132         self.set_errors(data.errors());  in set_from_data()
136         // All the bits are cleared to 0 on reset.  in reset()
142     fn default() -> Self {  in default()
151 /// This has the usual inbound RS232 modem-control signals, plus flags
157     /// DSR: Data set ready
159     /// DCD: Data carrier detect
162     /// busy transmitting data. QEMU's implementation never sets BUSY.
185     fn default() -> Self {  in default()
205     /// STP2: Two stop bits select
209     /// WLEN: Word length in bits
210     /// b11 = 8 bits
211     /// b10 = 7 bits
212     /// b01 = 6 bits
213     /// b00 = 5 bits.
217     /// 31:8 - Reserved, do not modify, read as zero.
224         // All the bits are cleared to 0 when reset.  in reset()
230     fn default() -> Self {  in default()
250     /// 1-byte-deep holding registers
260 /// These bits indicate the number of data bits transmitted or received in a
263     /// b11 = 8 bits
265     /// b10 = 7 bits
267     /// b01 = 6 bits
269     /// b00 = 5 bits.
276 /// enable bits, and the bits to write to set the usual outbound RS232
277 /// modem control signals. All bits reset to 0 except TXE and RXE.
287     /// `SIRLP` SIR low-power IrDA mode. QEMU does not model this.
297     /// `DTR` Data transmit ready
309     /// 31:16 - Reserved, do not modify, read as zero.
323     fn default() -> Self {  in default()
330 bits! {
331     /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
346         E = bits!(Self as u32: OE | BE | PE | FE),
347         MS = bits!(Self as u32: RI | DSR | DCD | CTS),