pl011/src/lib.rs

3 // SPDX-License-Identifier: GPL-2.0-or-later
57 /// ARM DDI 0183G, Table 3-1 p.3-3
82     /// `IrDA` Low-Power Counter Register
121     fn try_from(value: u64) -> Result<Self, Self::Error> {  in try_from()
148     //! All PL011 registers are essentially 32-bit wide, but are typed here as
151     //! as a 32-bit register where the unmentioned higher bits are always
162     /// - if the FIFOs are enabled, data written to this location is pushed onto
165     /// - if the FIFOs are not enabled, data is stored in the transmitter
170     /// prefixed with a start bit, appended with the appropriate parity bit
171     /// (if parity is enabled), and a stop bit. The resultant word is then
176     /// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
177     ///   frame, parity,
178     /// and overrun) is pushed onto the 12-bit wide receive FIFO
179     /// - if the FIFOs are not enabled, the data byte and status are stored in
215     /// information for break, framing and parity corresponds to the
251         fn default() -> Self {  in default()
277         /// becomes non-empty, regardless of whether the UART is enabled
323         fn default() -> Self {  in default()
335         /// 15:8 - Reserved, do not modify, read as zero.
337         /// 7 SPS Stick parity select.
338         /// 0 = stick parity is disabled
340         /// • if the EPS bit is 0 then the parity bit is transmitted and checked
341         /// as a 1 • if the EPS bit is 1 then the parity bit is
343         /// the PEN bit disables parity checking and generation. See Table 3-11
344         /// on page 3-14 for the parity truth table.
354         /// 1-byte-deep holding registers 1 = transmit and receive FIFO
361         /// EPS Even parity select. Controls the type of parity the UART uses
363         /// - 0 = odd parity. The UART generates or checks for an odd number of
364         ///   1s in the data and parity bits.
365         /// - 1 = even parity. The UART generates or checks for an even number
366         ///   of 1s in the data and parity bits.
367         /// This bit has no effect when the `PEN` bit disables parity checking
368         /// and generation. See Table 3-11 on page 3-14 for the parity
370         pub parity: Parity,  field
371         /// 1 PEN Parity enable:
373         /// - 0 = parity is disabled and no parity bit added to the data frame
374         /// - 1 = parity checking and generation is enabled.
376         /// See Table 3-11 on page 3-14 for the parity truth table.
380         /// If this bit is set to `1`, a low-level is continually output on the
396         fn default() -> Self {  in default()
403     /// `EPS` "Even parity select", field of [Line Control
405     pub enum Parity {  enum
406         /// - 0 = odd parity. The UART generates or checks for an odd number of
407         ///   1s in the data and parity bits.
408         Odd = 0,  enumerator
409         /// - 1 = even parity. The UART generates or checks for an even number
410         ///   of 1s in the data and parity bits.
420         /// 1-byte-deep holding registers
427         fn from(val: Mode) -> Self {  in from()
455     /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
474         /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding
475         /// mode. If this bit is cleared to 0, low-level bits are transmitted as
477         /// this bit is set to 1, low-level bits are transmitted with a pulse
486         /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
488         /// be set to 1 to override the normal half-duplex SIR operation. This
545         fn default() -> Self {  in default()