3 // SPDX-License-Identifier: GPL-2.0-or-later
45     fn index(&self, idx: hwaddr) -> &Self::Output {  in index()
90     ///  * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line)
91     ///  * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line)
131     /// Initializes a pre-allocated, unitialized instance of `PL011State`.
181     pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow<u64, u64> {  in read()
186                 u64::from(self.device_id[(offset - 0xfe0) >> 2])  in read()
196                     self.read_count -= 1;  in read()
197                     self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);  in read()
218                 // We exercise our self-control.  in read()
226                 // "The UARTICR Register is the interrupt clear register and is write-only"  in read()
275                 // Reset the FIFO state on FIFO enable or disable  in write()
335         // In real hardware, TX loopback happens at the serial-bit level  in loopback_tx()
336         // and then reassembled by the RX logics back into bytes and placed  in loopback_tx()
337         // into the RX fifo. That is, loopback happens after TX fifo.  in loopback_tx()
339         // Because the real hardware TX fifo is time-drained at the frame  in loopback_tx()
341         // bytes in TX fifo may still be able to get into the RX fifo  in loopback_tx()
345         // In such scenario, the RX draining pace is the major factor  in loopback_tx()
346         // deciding which loopback bytes get into the RX fifo, unless  in loopback_tx()
347         // hardware flow-control is enabled.  in loopback_tx()
359          * Loopback software-driven modem control outputs to modem status inputs:  in loopback_mdmctrl()
446         /* Reset FIFO flags */  in reset_fifo()
450     pub fn can_receive(&self) -> bool {  in can_receive()
451         // trace_pl011_can_receive(s->lcr, s->read_count, r);  in can_receive()
463     pub fn fifo_enabled(&self) -> bool {  in fifo_enabled()
464         matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO)  in fifo_enabled()
468     pub fn loopback_enabled(&self) -> bool {  in loopback_enabled()
473     pub fn fifo_depth(&self) -> usize {  in fifo_depth()
474         // Note: FIFO depth is expected to be power-of-2  in fifo_depth()
482         let depth = self.fifo_depth();  in put_fifo()  localVariable
483         assert!(depth > 0);  in put_fifo()
484         let slot = (self.read_pos + self.read_count) & (depth - 1);  in put_fifo()
488         if self.read_count == depth {  in put_fifo()
506     pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> {  in post_load()
507         /* Sanity-check input state */  in post_load()
514             // character in the FIFO in FIFO-disabled mode is in  in post_load()
535         | Interrupt::RX as u32,
536     Interrupt::RX as u32,
548 pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int {  in pl011_can_receive()
598 ) -> *mut DeviceState {  in pl011_create()
636 /// Initializes a pre-allocated, unitialized instance of `PL011Luminary`.