Lines Matching full:capability

56 #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
122 #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
208 /* Capability lists */
210 #define PCI_CAP_LIST_ID		0	/* Capability ID */
232 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
233 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
270 #define PCI_AGP_RFU		3	/* Rest of capability flags */
313 #define PCI_MSI_RFU		3	/* Rest of capability flags */
323 /* MSI-X registers (in MSI-X capability) */
371 #define PCI_EA_NUM_ENT		2	/* Number of Capability Entries */
461 #define  PCI_X_SSTATUS_VERS	0x3000	/* PCI-X Capability Version */
473 /* PCI Express capability registers */
476 #define  PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
553 #define  PCI_EXP_LNKCAP_LBNC	0x00200000 /* Link Bandwidth Notification Capability */
652  * are only present on devices with PCIe Capability version 2.
718 #define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
724 #define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
741 #define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
860 #define PCI_PWR_CAP		0x0c	/* Capability */
878  * HyperTransport sub capability types
880  * Unfortunately there are both 3 bit and 5 bit capability types defined
895 #define HT_CAPTYPE_MSI_MAPPING	0xA8	/* MSI Mapping Capability */
912 #define PCI_ARI_CAP		0x04	/* ARI Capability Register */
913 #define  PCI_ARI_CAP_MFVC	0x0001	/* MFVC Function Groups Capability */
914 #define  PCI_ARI_CAP_ACS	0x0002	/* ACS Function Groups Capability */
923 #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
999 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
1011 /* SATA capability */
1019 #define PCI_REBAR_CAP		4	/* capability register */
1029 #define PCI_DPA_CAP		4	/* capability register */
1039 #define PCI_TPH_CAP		4	/* capability register */
1046 #define   PCI_TPH_LOC_CAP	0x00000200 /* In capability */
1063 #define PCI_EXP_DPC_CAP			0x04	/* DPC Capability */
1103 #define PCI_PTM_CAP			0x04	    /* PTM Capability */
1148 /* Secondary PCIe Capability 8.0 GT/s */
1164 #define PCI_NPEM_CAP     0x04 /* NPEM capability register */
1172  * are corresponding for capability and control registers.