Lines Matching +full:8 +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * fourcc code, a Format Modifier may optionally be provided, in order to
43 * Format modifiers are used in conjunction with a fourcc code, forming a
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
61 * match only a single modifier. A modifier must not be a subset of layouts of
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
68 * a canonical pair needs to be defined and used by all drivers. Preferred
104 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ argument
116 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
127 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
128 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
139 /* 8 bpp Red (direct relationship between channel value and brightness) */
140 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
152 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
153 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
159 /* 8 bpp RGB */
160 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
161 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
169 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
170 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
171 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
172 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
179 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
180 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
181 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
182 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
192 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
193 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
194 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
195 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
197 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
198 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
199 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
200 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
207 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
208 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
209 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
210 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
213 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 littl…
214 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 littl…
216 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
217 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
227 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
228 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
234 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 1…
237 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little end…
238 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little end…
239 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little end…
240 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little end…
242 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
243 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endi…
244 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endi…
245 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endi…
246 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
261 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
262 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
263 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
267 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
271 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
273 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
275 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
287 * These formats can only be used with a non-Linear modifier.
289 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
293 * 2 plane RGB + A
295 * index 1 = A plane, [7:0] A
297 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
298 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
299 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
300 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
301 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
302 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
303 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
304 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
403 * Format modifiers describe, typically, a re-ordering or modification
404 * of the data in a plane of an FB. This can be used to express tiled/
405 * swizzled formats, or compression, or a combination of the two.
407 * The upper 8 bits of the format modifier are a vendor-id as assigned
440 * When adding a new token please document the layout with a code comment,
448 * compatibility, in cases where a vendor-specific definition already exists and
449 * a generic name for it is desired, the common name is a purely symbolic alias
456 * In future cases where a generic layout is identified before merging with a
457 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
460 * apply to a single vendor.
473 * This modifier can be used as a sentinel to terminate the format modifiers
474 * list, or to initialize a variable with an invalid modifier. It might also be
485 * and so might actually result in a tiled framebuffer.
494 * used is out-of-band information carried in an API-specific way (e.g. in a
504 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
506 * a platform-dependent stride. On top of that the memory can apply
509 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
511 * cross-driver sharing. It exists since on a given platform it does uniquely
512 * identify the layout in a simple way for i915-specific userspace, which
521 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
523 * chunks column-major, with a platform-dependent height. On top of that the
527 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
529 * cross-driver sharing. It exists since on a given platform it does uniquely
530 * identify the layout in a simple way for i915-specific userspace, which
539 * This is a tiled layout using 4Kb tiles in row-major layout.
545 * either a square block or a 2:1 unit.
554 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
558 * Each CCS tile matches a 1024x512 pixel area of the main surface.
563 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
564 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
575 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
576 * main surface. In other words, 4 bits in CCS map to a main surface cache
577 * line pair. The main surface pitch is required to be a multiple of four
586 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
587 * main surface. In other words, 4 bits in CCS map to a main surface cache
588 * line pair. The main surface pitch is required to be a multiple of four
608 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
610 * pitch is required to be a multiple of 4 tile widths.
612 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
617 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
620 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
621 * of 64B x 8 rows.
629 * outside of the GEM object in a reserved memory area dedicated for the
631 * main surface pitch is required to be a multiple of four Tile 4 widths.
641 * GEM object in a reserved memory area dedicated for the storage of the
643 * pitch is required to be a multiple of four Tile 4 widths.
651 * outside of the GEM object in a reserved memory area dedicated for the
653 * main surface pitch is required to be a multiple of four Tile 4 widths. The
665 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
666 * main surface. In other words, 4 bits in CCS map to a main surface cache
667 * line pair. The main surface pitch is required to be a multiple of four
676 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
677 * main surface. In other words, 4 bits in CCS map to a main surface cache
678 * line pair. The main surface pitch is required to be a multiple of four
698 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
700 * pitch is required to be a multiple of 4 tile widths.
711 * GEM object in a reserved memory area dedicated for the storage of the
723 * GEM object in a reserved memory area dedicated for the storage of the
725 * contiguous memory with a size aligned to 64KB
732 * Macroblocks are laid in a Z-shape, and each pixel data is following the
747 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
748 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
756 * Refers to a compressed variant of the base format that is compressed.
793 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
801 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
802 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
813 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
823 * starts at a different base address. Offsets from the base addresses are
830 * the color buffer tiling modifiers defined above. When TS is present it's a
835 * We reserve the top 8 bits of the Vivante modifier space for tile status
846 * Vivante compression modifiers. Those depend on a TS modifier being present
872 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
874 * a block depth or height of "4").
891 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
895 * hardware support a block width of two gobs, but it is impractical
903 * 19:12 k Page Kind. This value directly maps to a field in the page
916 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
920 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
922 * 2 = Gob Height 8, Turing+ Page Kind mapping
925 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
976 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
978 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1012 * type, and the next 24 bits for parameters. Top 8 bits are the
1015 #define __fourcc_mod_broadcom_param_shift 8
1032 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1035 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1038 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1066 * and UV. Some SAND-using hardware stores UV in a separate tiled
1072 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1109 * necessary to reduce the padding. If a hardware block can't do XOR,
1110 * the assumption is that a no-XOR tiling modifier will be created.
1117 * AFBC is a proprietary lossless image compression protocol and format.
1132 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1148 * size (in pixels) must be aligned to a multiple of the superblock size.
1175 * half of the payload is positioned at a predefined offset from the start
1183 * This flag indicates that the payload of each superblock must be stored at a
1196 * is such that there are no copy-blocks referring across the border of 8x8
1197 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1204 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1205 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1211 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1217 * can be reduced if a whole superblock is a single color.
1224 * Indicates that the buffer is allocated in a layout safe for front-buffer
1242 * affects the storage mode of the individual superblocks. Note that even a
1251 * AFRC is a proprietary fixed rate image compression protocol and format,
1259 * "coding unit" blocks which are individually compressed to a
1260 * fixed size (in bytes). All coding units within a given plane of a buffer
1275 * to a multiple of the paging tile dimensions.
1282 * ROT 8 coding units 8 coding units
1291 * Example: 16x4 luma samples in a 'Y' plane
1292 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1294 * 1 ROT 8 samples 8 samples
1295 * Example: 8x8 luma samples in a 'Y' plane
1296 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1298 * 2 DONT CARE 8 samples 4 samples
1299 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1349 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1365 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1378 * Amlogic uses a proprietary lossless image compression protocol and format
1385 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1390 * The first 8 bits of the mode defines the layout, then the following 8 bits
1397 #define __fourcc_mod_amlogic_options_shift 8
1412 * - a body content organized in 64x32 superblocks with 4096 bytes per
1414 * - a 32 bytes per 128x64 header block
1435 * The user-space clients should expect a failure while trying to mmap
1446 * boundaries, i.e. 8bit should be stored in this mode to save allocation
1479 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1544 #define AMD_FMT_MOD_TILE_SHIFT 8
1572 * and prefers the driver provided color. This necessitates doing a fastclear
1573 * eliminate operation before a process transfers control.