hw/sd/allwinner-sdhost.h

61 struct AwSdHostState {  struct
63     SysBusDevice busdev;
67     SDBus sdbus;
70     MemoryRegion iomem;
73     qemu_irq irq;
76     MemoryRegion *dma_mr;
79     AddressSpace dma_as;
82     uint32_t transfer_cnt;
89     uint32_t global_ctl;        /**< Global Control */
90     uint32_t clock_ctl;         /**< Clock Control */
91     uint32_t timeout;           /**< Timeout */
92     uint32_t bus_width;         /**< Bus Width */
93     uint32_t block_size;        /**< Block Size */
94     uint32_t byte_count;        /**< Byte Count */
96     uint32_t command;           /**< Command */
97     uint32_t command_arg;       /**< Command Argument */
98     uint32_t response[4];       /**< Command Response */
100     uint32_t irq_mask;          /**< Interrupt Mask */
101     uint32_t irq_status;        /**< Raw Interrupt Status */
102     uint32_t status;            /**< Status */
104     uint32_t fifo_wlevel;       /**< FIFO Water Level */
105     uint32_t fifo_func_sel;     /**< FIFO Function Select */
106     uint32_t debug_enable;      /**< Debug Enable */
107     uint32_t auto12_arg;        /**< Auto Command 12 Argument */
108     uint32_t newtiming_set;     /**< SD New Timing Set */
109     uint32_t newtiming_debug;   /**< SD New Timing Debug */
110     uint32_t hardware_rst;      /**< Hardware Reset */
111     uint32_t dmac;              /**< Internal DMA Controller Control */
112     uint32_t desc_base;         /**< Descriptor List Base Address */
113     uint32_t dmac_status;       /**< Internal DMA Controller Status */
114     uint32_t dmac_irq;          /**< Internal DMA Controller IRQ Enable */
115     uint32_t card_threshold;    /**< Card Threshold Control */
116     uint32_t startbit_detect;   /**< eMMC DDR Start Bit Detection Control */
117     uint32_t response_crc;      /**< Response CRC */
118     uint32_t data_crc[8];       /**< Data CRC */
119     uint32_t sample_delay;      /**< Sample delay control */
120     uint32_t status_crc;        /**< Status CRC */