Lines Matching refs:PPC_BITMASK32
23 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
26 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
29 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
71 #define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
72 #define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
73 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
75 #define END2_W1_ESn PPC_BITMASK32(0, 1)
78 #define END2_W1_ESe PPC_BITMASK32(2, 3)
83 #define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
85 #define END2_W2_RESERVED PPC_BITMASK32(4, 7)
86 #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
88 #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24)
89 #define END2_W3_QSIZE PPC_BITMASK32(28, 31)
91 #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
92 #define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
93 #define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3)
94 #define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
96 #define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
101 #define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
102 #define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
103 #define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
105 #define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */
106 #define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
107 #define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
156 #define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
158 #define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
160 #define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
161 #define NVP2_W2_IPB PPC_BITMASK32(8, 15)
162 #define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
165 #define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
166 #define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
167 #define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
168 #define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
170 #define NVP2_W5_PSIZE PPC_BITMASK32(0, 1)
171 #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
172 #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)