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24 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
27 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
30 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
46 #define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
77 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
87 #define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
90 #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
94 #define END2_W3_QSIZE PPC_BITMASK32(28, 31)
97 #define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
99 #define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
101 #define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
107 #define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
108 #define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
112 #define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
163 #define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31)
168 #define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
174 #define NVP2_W2_LGS PPC_BITMASK32(28, 31)
178 #define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
180 #define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
184 #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
186 #define NVP2_W6_REPORTING_LINE PPC_BITMASK32(4, 31)
226 #define NVGC2_W0_PGONEXT PPC_BITMASK32(26, 31)
230 #define NVGC2_W1_END_IDX PPC_BITMASK32(8, 31)