29 #define TYPE_PNV_CHIP "pnv-chip"
60 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
61 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
112 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
132 #define PNV_XSCOM_BASE(chip)                                            \  argument
133     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
137 #define PNV_OCC_SENSOR_BASE(chip)   (PNV_OCC_COMMON_AREA_BASE + \  argument
138     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
141 #define PNV_HOMER_BASE(chip)                                            \  argument
142     (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
160 #define PNV_ICP_BASE(chip)                                              \  argument
161     (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
165 #define PNV_PSIHB_BASE(chip) \  argument
166     (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
169 #define PNV_PSIHB_FSP_BASE(chip) \  argument
170     (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
176 #define PNV9_CHIP_BASE(chip, base)   \  argument
177     ((base) + ((uint64_t) (chip)->chip_id << 42))
180 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)  argument
183 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)  argument
186 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)  argument
189 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)  argument
192 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)  argument
195 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)  argument
198 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)  argument
201 #define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)  argument
205 #define PNV9_OCC_SENSOR_BASE(chip)   (PNV9_OCC_COMMON_AREA_BASE +       \  argument
206     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
208 #define PNV9_HOMER_BASE(chip)                                           \  argument
209     (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
212  * POWER10 MMIO base addresses - 16TB stride per chip
214 #define PNV10_CHIP_BASE(chip, base)   \  argument
215     ((base) + ((uint64_t) (chip)->chip_id << 44))
218 #define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)  argument
221 #define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)  argument
224 #define PNV10_XIVE2_IC_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030200000000ull)  argument
227 #define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)  argument
230 #define PNV10_PSIHB_BASE(chip)      PNV10_CHIP_BASE(chip, 0x0006030203000000ull)  argument
233 #define PNV10_XIVE2_TM_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030203180000ull)  argument
236 #define PNV10_XIVE2_NVC_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030208000000ull)  argument
239 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)  argument
242 #define PNV10_XIVE2_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006050000000000ull)  argument
245 #define PNV10_XIVE2_END_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006060000000000ull)  argument
249 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE +       \  argument
250     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
252 #define PNV10_HOMER_BASE(chip)                                           \  argument
253     (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)