Lines Matching +full:0 +full:x0700
53 #define DBDMA_CONTROL 0x00
54 #define DBDMA_STATUS 0x01
55 #define DBDMA_CMDPTR_HI 0x02
56 #define DBDMA_CMDPTR_LO 0x03
57 #define DBDMA_INTR_SEL 0x04
58 #define DBDMA_BRANCH_SEL 0x05
59 #define DBDMA_WAIT_SEL 0x06
60 #define DBDMA_XFER_MODE 0x07
61 #define DBDMA_DATA2PTR_HI 0x08
62 #define DBDMA_DATA2PTR_LO 0x09
63 #define DBDMA_RES1 0x0A
64 #define DBDMA_ADDRESS_HI 0x0B
65 #define DBDMA_BRANCH_ADDR_HI 0x0C
66 #define DBDMA_RES2 0x0D
67 #define DBDMA_RES3 0x0E
68 #define DBDMA_RES4 0x0F
76 #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
80 #define RUN 0x8000
81 #define PAUSE 0x4000
82 #define FLUSH 0x2000
83 #define WAKE 0x1000
84 #define DEAD 0x0800
85 #define ACTIVE 0x0400
86 #define BT 0x0100
87 #define DEVSTAT 0x00ff
104 #define COMMAND_MASK 0xf000
105 #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
106 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
107 #define INPUT_MORE 0x2000 /* transfer stream data to memory */
108 #define INPUT_LAST 0x3000 /* ditto, expect end marker */
109 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
110 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
111 #define DBDMA_NOP 0x6000 /* do nothing */
112 #define DBDMA_STOP 0x7000 /* suspend processing */
116 #define KEY_MASK 0x0700
117 #define KEY_STREAM0 0x0000 /* usual data stream */
118 #define KEY_STREAM1 0x0100 /* control/status stream */
119 #define KEY_STREAM2 0x0200 /* device-dependent stream */
120 #define KEY_STREAM3 0x0300 /* device-dependent stream */
121 #define KEY_STREAM4 0x0400 /* reserved */
122 #define KEY_REGS 0x0500 /* device register space */
123 #define KEY_SYSTEM 0x0600 /* system memory-mapped space */
124 #define KEY_DEVICE 0x0700 /* device memory-mapped space */
128 #define INTR_MASK 0x0030
129 #define INTR_NEVER 0x0000 /* don't interrupt */
130 #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
131 #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
132 #define INTR_ALWAYS 0x0030 /* always interrupt */
136 #define BR_MASK 0x000c
137 #define BR_NEVER 0x0000 /* don't branch */
138 #define BR_IFSET 0x0004 /* branch if condition bit is 1 */
139 #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
140 #define BR_ALWAYS 0x000c /* always branch */
144 #define WAIT_MASK 0x0003
145 #define WAIT_NEVER 0x0000 /* don't wait */
146 #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
147 #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
148 #define WAIT_ALWAYS 0x0003 /* always wait */