Lines Matching defs:AwSun8iEmacState
40 struct AwSun8iEmacState { struct
42 SysBusDevice parent_obj;
46 MemoryRegion iomem;
49 qemu_irq irq;
52 MemoryRegion *dma_mr;
55 AddressSpace dma_as;
58 NICState *nic;
61 NICConf conf;
68 uint8_t mii_phy_addr; /**< PHY address */
69 uint32_t mii_cr; /**< Control */
70 uint32_t mii_st; /**< Status */
71 uint32_t mii_adv; /**< Advertised Abilities */
80 uint32_t basic_ctl0; /**< Basic Control 0 */
81 uint32_t basic_ctl1; /**< Basic Control 1 */
82 uint32_t int_en; /**< Interrupt Enable */
83 uint32_t int_sta; /**< Interrupt Status */
84 uint32_t frm_flt; /**< Receive Frame Filter */
86 uint32_t rx_ctl0; /**< Receive Control 0 */
87 uint32_t rx_ctl1; /**< Receive Control 1 */
88 uint32_t rx_desc_head; /**< Receive Descriptor List Address */
89 uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
91 uint32_t tx_ctl0; /**< Transmit Control 0 */
92 uint32_t tx_ctl1; /**< Transmit Control 1 */
93 uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
94 uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
95 uint32_t tx_flowctl; /**< Transmit Flow Control */
97 uint32_t mii_cmd; /**< Management Interface Command */
98 uint32_t mii_data; /**< Management Interface Data */