Lines Matching +full:input +full:- +full:sel

31 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
33 /* Maximum amount of clock inputs in a SEL module. */
45 /* SEL/MUX in CLK module. */
88  * struct NPCM7xxClockPLLState - A PLL module in CLK module.
91  * @clock_in: The input clock of this module.
107  * struct NPCM7xxClockSELState - A SEL module in CLK module.
111  * @clock_in: The input clocks of this module.
130  * struct NPCM7xxClockDividerState - A Divider module in CLK module.
133  * @clock_in: The input clock of this module.
135  * @divide: The function the divider uses to divide the input.
190 #define TYPE_NPCM_CLK "npcm-clk"
192 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
193 #define TYPE_NPCM8XX_CLK "npcm8xx-clk"