Lines Matching full:module

33 /* Maximum amount of clock inputs in a SEL module. */
36 /* PLLs in CLK module. */
45 /* SEL/MUX in CLK module. */
59 /* Dividers in CLK module. */
88  * struct NPCM7xxClockPLLState - A PLL module in CLK module.
89  * @name: The name of the module.
90  * @clk: The CLK module that owns this module.
91  * @clock_in: The input clock of this module.
92  * @clock_out: The output clock of this module.
93  * @reg: The control registers for this PLL module.
107  * struct NPCM7xxClockSELState - A SEL module in CLK module.
108  * @name: The name of the module.
109  * @clk: The CLK module that owns this module.
110  * @input_size: The size of inputs of this module.
111  * @clock_in: The input clocks of this module.
112  * @clock_out: The output clocks of this module.
113  * @offset: The offset of this module in the control register.
114  * @len: The length of this module in the control register.
130  * struct NPCM7xxClockDividerState - A Divider module in CLK module.
131  * @name: The name of the module.
132  * @clk: The CLK module that owns this module.
133  * @clock_in: The input clock of this module.
134  * @clock_out: The output clock of this module.