hw/misc/aspeed_scu.h

9  * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84  *    arch/arm/mach-aspeed/include/mach/regs-scu.h
86  *    Copyright (C) 2012-2020  ASPEED Technology Inc.
103  *  25:23  APB PCLK divider selection
106  *  18:16  MAC AHB bus clock divider selection
117 #define SCU_CLK_GET_PCLK_DIV(x)                    (((x) >> 23) & 0x7)
120  * SCU24   H-PLL Parameter Register (for Aspeed AST2400 SOC)
122  *  18     H-PLL parameter selection
123  *           0: Select H-PLL by strapping resistors
124  *           1: Select H-PLL by the programmed registers (SCU24[17:0])
125  *  17     Enable H-PLL bypass mode
126  *  16     Turn off H-PLL
127  *  10:5   H-PLL Numerator
128  *  4      H-PLL Output Divider
129  *  3:0    H-PLL Denumerator
131  *  (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
134 #define SCU_AST2400_H_PLL_PROGRAMMED               (0x1 << 18)
139  * SCU24   H-PLL Parameter Register (for Aspeed AST2500 SOC)
141  *  21     Enable H-PLL reset
142  *  20     Enable H-PLL bypass mode
143  *  19     Turn off H-PLL
144  *  18:13  H-PLL Post Divider
145  *  12:5   H-PLL Numerator (M)
146  *  4:0    H-PLL Denumerator (N)
162  * 23     Enable 25 MHz reference clock input
163  * 22     Enable GPIOE pass-through mode
164  * 21     Enable GPIOD pass-through mode
167  * 23,18  Clock source selection
174  * 9:8    H-PLL default clock frequency selection
200 /* bit 23, 18 [1,0] */
201 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x)     (((((x) & 0x3) >> 1) << 23) \
202                                                     | (((x) & 0x1) << 18))
203 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x)     (((((x) >> 23) & 0x1) << 1) \
204                                                     | (((x) >> 18) & 0x1))
205 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK       ((0x1 << 23) | (0x1 << 18))
206 #define SCU_HW_STRAP_CLK_25M_IN                    (0x1 << 23)
212 #define SCU_HW_STRAP_CLK_48M_IN                    (0x1 << 18)
271  * 23     Select 25 MHz reference clock input mode
272  * 22     Enable GPIOE pass-through mode
273  * 21     Enable GPIOD pass-through mode
276  * 18     Select USBCKI input frequency
303 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE       (0x1 << 23)
306 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ           (0x1 << 18)
335  * SCU200   H-PLL Parameter Register (for Aspeed AST2600 SOC)
337  *  28:26  H-PLL Parameters
338  *  25     Enable H-PLL reset
339  *  24     Enable H-PLL bypass mode
340  *  23     Turn off H-PLL
341  *  22:19  H-PLL Post Divider (P)
342  *  18:13  H-PLL Numerator (M)
343  *  12:0   H-PLL Denumerator (N)
350 #define SCU_AST2600_H_PLL_OFF                              (0x1 << 23)
385  *  23:21  RMIICLK_DIV
386  *  20:18  PCLK_DIV
403 #define SCUIO_AST2700_CLK_GET_PCLK_DIV(x)                    (((x) >> 18) & 0x7)