hw/i386/intel_iommu.h

2  * QEMU emulation of an Intel IOMMU (VT-d)
25 #include "hw/i386/x86-iommu.h"
26 #include "qemu/iova-tree.h"
29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
49 #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
66 /* Context-Entry */
136      * registered drivers (e.g. vfio-pci) on either:
139      *       VFIO_IOMMU_MAP_DMA, -EEXIST will trigger), or,
143      * That accuracy is not required for UNMAP-only notifiers, but it is a
144      * must-to-have for notifiers registered with MAP events, because the
160 /* VT-d Source-ID Qualifier types */
165     VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
169 /* VT-d Source Validation Types */
186         uint64_t __avail:4;          /* Available spaces for software */
200         uint64_t __avail:4;          /* Available spaces for software */
209         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
210         uint64_t sid_q:2;            /* Source-ID Qualifier */
211         uint64_t source_id:16;       /* Source-ID */
213         uint64_t source_id:16;       /* Source-ID */
214         uint64_t sid_q:2;            /* Source-ID Qualifier */
215         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
225 /* Programming format for MSI/MSI-X addresses */
230         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
232         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
238         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
240         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
247 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
260     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
263     bool caching_mode;              /* RO - is cap CM enabled? */
264     bool scalable_mode;             /* RO - is Scalable Mode supported? */
265     bool snoop_control;             /* RO - is SNP filed supported? */
280      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
290     GHashTable *vtd_address_spaces;             /* VTD address spaces */
314      * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.