Lines Matching +full:0 +full:xff9d0000
174 #define MM_TOP_RSVD 0xa0000000U
175 #define MM_TOP_RSVD_SIZE 0x4000000
176 #define MM_GIC_APU_DIST_MAIN 0xf9000000U
177 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
178 #define MM_GIC_APU_REDIST_0 0xf9080000U
179 #define MM_GIC_APU_REDIST_0_SIZE 0x80000
181 #define MM_UART0 0xff000000U
182 #define MM_UART0_SIZE 0x10000
183 #define MM_UART1 0xff010000U
184 #define MM_UART1_SIZE 0x10000
186 #define MM_CANFD0 0xff060000U
187 #define MM_CANFD0_SIZE 0x10000
188 #define MM_CANFD1 0xff070000U
189 #define MM_CANFD1_SIZE 0x10000
191 #define MM_GEM0 0xff0c0000U
192 #define MM_GEM0_SIZE 0x10000
193 #define MM_GEM1 0xff0d0000U
194 #define MM_GEM1_SIZE 0x10000
196 #define MM_ADMA_CH0 0xffa80000U
197 #define MM_ADMA_CH0_SIZE 0x10000
199 #define MM_OCM 0xfffc0000U
200 #define MM_OCM_SIZE 0x40000
202 #define MM_XRAM 0xfe800000
203 #define MM_XRAMC 0xff8e0000
204 #define MM_XRAMC_SIZE 0x10000
206 #define MM_USB2_CTRL_REGS 0xFF9D0000
207 #define MM_USB2_CTRL_REGS_SIZE 0x10000
209 #define MM_USB_0 0xFE200000
210 #define MM_USB_0_SIZE 0x10000
212 #define MM_TOP_DDR 0x0
213 #define MM_TOP_DDR_SIZE 0x80000000U
214 #define MM_TOP_DDR_2 0x800000000ULL
215 #define MM_TOP_DDR_2_SIZE 0x800000000ULL
216 #define MM_TOP_DDR_3 0xc000000000ULL
217 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL
218 #define MM_TOP_DDR_4 0x10000000000ULL
219 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL
221 #define MM_PSM_START 0xffc80000U
222 #define MM_PSM_END 0xffcf0000U
224 #define MM_CRL 0xff5e0000U
225 #define MM_CRL_SIZE 0x300000
226 #define MM_IOU_SCNTR 0xff130000U
227 #define MM_IOU_SCNTR_SIZE 0x10000
228 #define MM_IOU_SCNTRS 0xff140000U
229 #define MM_IOU_SCNTRS_SIZE 0x10000
230 #define MM_FPD_CRF 0xfd1a0000U
231 #define MM_FPD_CRF_SIZE 0x140000
232 #define MM_FPD_FPD_APU 0xfd5c0000
233 #define MM_FPD_FPD_APU_SIZE 0x100
235 #define MM_PMC_PMC_IOU_SLCR 0xf1060000
236 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
238 #define MM_PMC_OSPI 0xf1010000
239 #define MM_PMC_OSPI_SIZE 0x10000
241 #define MM_PMC_OSPI_DAC 0xc0000000
242 #define MM_PMC_OSPI_DAC_SIZE 0x20000000
244 #define MM_PMC_OSPI_DMA_DST 0xf1011800
245 #define MM_PMC_OSPI_DMA_SRC 0xf1011000
247 #define MM_PMC_SD0 0xf1040000U
248 #define MM_PMC_SD0_SIZE 0x10000
249 #define MM_PMC_BBRAM_CTRL 0xf11f0000
250 #define MM_PMC_BBRAM_CTRL_SIZE 0x00050
251 #define MM_PMC_EFUSE_CTRL 0xf1240000
252 #define MM_PMC_EFUSE_CTRL_SIZE 0x00104
253 #define MM_PMC_EFUSE_CACHE 0xf1250000
254 #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
256 #define MM_PMC_CFU_APB 0xf12b0000
257 #define MM_PMC_CFU_APB_SIZE 0x10000
258 #define MM_PMC_CFU_STREAM 0xf12c0000
259 #define MM_PMC_CFU_STREAM_SIZE 0x1000
260 #define MM_PMC_CFU_SFR 0xf12c1000
261 #define MM_PMC_CFU_SFR_SIZE 0x1000
262 #define MM_PMC_CFU_FDRO 0xf12c2000
263 #define MM_PMC_CFU_FDRO_SIZE 0x1000
264 #define MM_PMC_CFU_STREAM_2 0xf1f80000
265 #define MM_PMC_CFU_STREAM_2_SIZE 0x40000
267 #define MM_PMC_CFRAME0_REG 0xf12d0000
268 #define MM_PMC_CFRAME0_REG_SIZE 0x1000
269 #define MM_PMC_CFRAME0_FDRI 0xf12d1000
270 #define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
271 #define MM_PMC_CFRAME1_REG 0xf12d2000
272 #define MM_PMC_CFRAME1_REG_SIZE 0x1000
273 #define MM_PMC_CFRAME1_FDRI 0xf12d3000
274 #define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
275 #define MM_PMC_CFRAME2_REG 0xf12d4000
276 #define MM_PMC_CFRAME2_REG_SIZE 0x1000
277 #define MM_PMC_CFRAME2_FDRI 0xf12d5000
278 #define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
279 #define MM_PMC_CFRAME3_REG 0xf12d6000
280 #define MM_PMC_CFRAME3_REG_SIZE 0x1000
281 #define MM_PMC_CFRAME3_FDRI 0xf12d7000
282 #define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
283 #define MM_PMC_CFRAME4_REG 0xf12d8000
284 #define MM_PMC_CFRAME4_REG_SIZE 0x1000
285 #define MM_PMC_CFRAME4_FDRI 0xf12d9000
286 #define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
287 #define MM_PMC_CFRAME5_REG 0xf12da000
288 #define MM_PMC_CFRAME5_REG_SIZE 0x1000
289 #define MM_PMC_CFRAME5_FDRI 0xf12db000
290 #define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
291 #define MM_PMC_CFRAME6_REG 0xf12dc000
292 #define MM_PMC_CFRAME6_REG_SIZE 0x1000
293 #define MM_PMC_CFRAME6_FDRI 0xf12dd000
294 #define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
295 #define MM_PMC_CFRAME7_REG 0xf12de000
296 #define MM_PMC_CFRAME7_REG_SIZE 0x1000
297 #define MM_PMC_CFRAME7_FDRI 0xf12df000
298 #define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
299 #define MM_PMC_CFRAME8_REG 0xf12e0000
300 #define MM_PMC_CFRAME8_REG_SIZE 0x1000
301 #define MM_PMC_CFRAME8_FDRI 0xf12e1000
302 #define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
303 #define MM_PMC_CFRAME9_REG 0xf12e2000
304 #define MM_PMC_CFRAME9_REG_SIZE 0x1000
305 #define MM_PMC_CFRAME9_FDRI 0xf12e3000
306 #define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
307 #define MM_PMC_CFRAME10_REG 0xf12e4000
308 #define MM_PMC_CFRAME10_REG_SIZE 0x1000
309 #define MM_PMC_CFRAME10_FDRI 0xf12e5000
310 #define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
311 #define MM_PMC_CFRAME11_REG 0xf12e6000
312 #define MM_PMC_CFRAME11_REG_SIZE 0x1000
313 #define MM_PMC_CFRAME11_FDRI 0xf12e7000
314 #define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
315 #define MM_PMC_CFRAME12_REG 0xf12e8000
316 #define MM_PMC_CFRAME12_REG_SIZE 0x1000
317 #define MM_PMC_CFRAME12_FDRI 0xf12e9000
318 #define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
319 #define MM_PMC_CFRAME13_REG 0xf12ea000
320 #define MM_PMC_CFRAME13_REG_SIZE 0x1000
321 #define MM_PMC_CFRAME13_FDRI 0xf12eb000
322 #define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
323 #define MM_PMC_CFRAME14_REG 0xf12ec000
324 #define MM_PMC_CFRAME14_REG_SIZE 0x1000
325 #define MM_PMC_CFRAME14_FDRI 0xf12ed000
326 #define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
327 #define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
328 #define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
329 #define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
330 #define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
332 #define MM_PMC_CRP 0xf1260000U
333 #define MM_PMC_CRP_SIZE 0x10000
334 #define MM_PMC_RTC 0xf12a0000
335 #define MM_PMC_RTC_SIZE 0x10000
336 #define MM_PMC_TRNG 0xf1230000
337 #define MM_PMC_TRNG_SIZE 0x10000