hw/arm/armsse.h

2  * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
8  * it under the terms of the GNU General Public License version 2 or
14  * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
15  * SSE-200. Currently we model:
16  *  - the Arm IoT Kit which is documented in
18  *  - the SSE-200 which is documented in
22  *  a Cortex-M33
29  *  space are secure and non-secure aliases of each other
30  * The SSE-200 additionally contains:
31  *  a second Cortex-M33
37  *  per-CPU identity and control register blocks
45  *    (In hardware, the SSE-200 permits the number of expansion interrupts
52  *  + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
57  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
68  *    all the devices and memory areas in the IoTKit
71  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
72  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
73  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
74  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
75  *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
78  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
79  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
80  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
81  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
82  *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
89  *  + named GPIO outputs mscexp_clear[0..15]
90  *  + named GPIO outputs mscexp_ns[0..15]
98 #include "hw/misc/iotkit-secctl.h"
99 #include "hw/misc/tz-ppc.h"
100 #include "hw/misc/tz-mpc.h"
101 #include "hw/timer/cmsdk-apb-timer.h"
102 #include "hw/timer/cmsdk-apb-dualtimer.h"
103 #include "hw/timer/sse-counter.h"
104 #include "hw/timer/sse-timer.h"
105 #include "hw/watchdog/cmsdk-apb-watchdog.h"
106 #include "hw/misc/iotkit-sysctl.h"
107 #include "hw/misc/iotkit-sysinfo.h"
108 #include "hw/misc/armsse-cpuid.h"
109 #include "hw/misc/armsse-mhu.h"
110 #include "hw/misc/armsse-cpu-pwrctrl.h"
112 #include "hw/or-irq.h"
114 #include "hw/core/split-irq.h"
118 #define TYPE_ARM_SSE "arm-sse"
128 #define TYPE_SSE200 "sse-200"
129 #define TYPE_SSE300 "sse-300"
132  * and the 2 internal PPCs
134 #define NUM_INTERNAL_PPCS 2
143 #define SSE_MAX_CPUS 2
180     ARMSSEMHU mhu[2];
190      * 'container' holds all devices seen by all CPUs.
192      * per-CPU devices of that CPU, plus as the background 'container'
198     MemoryRegion container_alias[SSE_MAX_CPUS - 1];